Datasheet
Section 6 Power-Down Modes 
Rev.5.00 Nov. 02, 2005 Page 86 of 500 
REJ09B0027-0500   
6.4 Direct Transition 
The CPU can execute programs in two modes: active and subactive modes. A direct transition is a 
transition between these two modes without stopping program execution. A direct transition can 
be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct 
transition also enables operating frequency modification in active or subactive mode. After the 
mode transition, direct transition interrupt exception handling starts. 
If the direct transition interrupt is disabled in interrupt enable register 1, a transition is made 
instead to sleep or subsleep mode. Note that if a direct transition is attempted while the I bit in 
CCR is set to 1, sleep or subsleep mode will be entered, and the resulting mode cannot be cleared 
by means of an interrupt. 
6.4.1  Direct Transition from Active Mode to Subactive Mode 
The time from the start of SLEEP instruction execution to the end of interrupt exception handling 
(the direct transition time) is calculated by equation (1). 
Direct transition time = {(number of SLEEP instruction execution states) + (number of internal 
processing states)}× (tcyc before transition) + (number of interrupt exception handling states) × 
(tsubcyc after transition)   (1) 
Example 
Direct transition time = (2 + 1) × tosc + 14 × 8tw = 3tosc + 112tw 
(when the CPU operating clock of φ
osc
 → φ
w
/8 is selected) 
Legend 
tosc: OSC clock cycle time 
tw: Watch clock cycle time 
tcyc: System clock (φ) cycle time 
tsubcyc: Subclock (φ
SUB
) cycle time 
6.4.2  Direct Transition from Subactive Mode to Active Mode 
The time from the start of SLEEP instruction execution to the end of interrupt exception handling 
(the direct transition time) is calculated by equation (2). 
Direct transition time = {(number of SLEEP instruction execution states) + (number of internal 
processing states)} × (tsubcyc before transition) + {(waiting time set in bits STS2 to STS0) + 
(number of interrupt exception handling states)} × (tcyc after transition)   (2) 










