Datasheet

Section 5 Clock Pulse Generators
CPG0300A_000020020300 Rev.4.00 Nov. 02, 2005 Page 65 of 304
REJ09B0143-0400
Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including a system
clock pulse generator. The system clock pulse generator consists of a system clock oscillator, a
duty correction circuit, and system clock dividers.
Figure 5.1 shows a block diagram of the clock pulse generators.
System
clock
oscillator
Duty
correction
circuit
System
clock
divider
Prescaler S
(13 bits)
OSC
1
OSC
2
System clock pulse generator
φ
OSC
(φ
OSC
)
φ
OSC
(φ
OSC
)
φ/2
to
φ/8192
φ
φ
OSC
/8
φ
OSC
φ
OSC
/16
φ
OSC
/32
φ
OSC
/64
Figure 5.1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are ø.
The system clock is divided into ø/8192 to ø/2 by prescaler S and they are supplied to respective
peripheral modules.
5.1 System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system
clock generator.
LPM
LPM: Low-power mode (standby mode, subsleep mode)
2
1
OSC
OSC
Figure 5.2 Block Diagram of System Clock Generator