Datasheet

Section 4 Address Break
Rev.4.00 Nov. 02, 2005 Page 57 of 304
REJ09B0143-0400
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 16.1,
Register Addresses (Address Order).
Table 4.1 Access and Data Bus Used
Word Access Byte Access
Even Address Odd Address Even Address Odd Address
ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
I/O register with 8-bit data
bus width
Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits
I/O register with 16-bit data
bus width
Upper 8 bits Lower 8 bits — —
4.1.2 Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit Bit Name Initial Value R/W Description
7 ABIF 0 R/W Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
6 ABIE 0 R/W Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
5 to 0 — All 1 — Reserved
These bits are always read as 1.