Datasheet

Section 3 Exception Handling
Rev.4.00 Nov. 02, 2005 Page 42 of 304
REJ09B0143-0400
3.1 Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1 Exception Sources and Vector Address
Relative Module Exception Sources
Vector
Number Vector Address Priority
RES pin
Watchdog timer
Reset 0 H'0000 to H'0001 High
 Reserved for system use 1 to 6 H'0002 to H'000D
External interrupt
pin
NMI 7 H'000E to H'000F
Trap instruction (#0) 8 H'0010 to H'0011
(#1) 9 H'0012 to H'0013
(#2) 10 H'0014 to H'0015
CPU
(#3) 11 H'0016 to H'0017
Address break Break conditions satisfied 12 H'0018 to H'0019
CPU Direct transition by executing the
SLEEP instruction
13 H'001A to H'001B
IRQ0 14 H'001C to H'001D
IRQ3 17 H'0022 to H'0023
External interrupt
pin
WKP 18 H'0024 to H'0025
 Reserved for system use 20 H'0028 to H'0029
Timer W Input capture A/compare match A
Input capture B/compare match B
Input capture C/compare match C
Input capture D/compare match D
Timer W overflow
21 H'002A to H'002B
Timer V Timer V compare match A
Timer V compare match B
Timer V overflow
22 H'002C to H'002D
SCI3 SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
23 H'002E to H'002F
A/D converter A/D conversion end 25 H'0032 to H'0033 Low