Datasheet

Section 2 CPU
Rev.4.00 Nov. 02, 2005 Page 32 of 304
REJ09B0143-0400
2.6 Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φ
SUB
). The period from a rising
edge of φ or φ
SUB
to the next rising edge is called one state. A bus cycle consists of two states or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
T
1
state
Bus cycle
T
2
state
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Read data
Address
Write data
Internal data bus
(write access)
SUB
φ or φ
Figure 2.9 On-Chip Memory Access Cycle