Datasheet

Rev.4.00 Nov. 02, 2005 Page 298 of 304
REJ09B0143-0400
Item Page Revisions (See Manual for Details)
Section 2 CPU
Figure 2.1 Memory Map
8
Interrupt vector
Not used
H'0000
H'0033
H'0034
H'3FFF
H'4000
H'4FFF
H'4000
H'4FFF
H'F780 H'F780
HD64F3672
(Flash memory version)
HD64F3670
(Flash memory version)
Interrupt vector
On-chip ROM
(8 kbytes)
On-chip ROM
(16 kbytes)
Not used
H'0000
H'0033
H'0034
H'1FFF
E7 or E8 control
program area
(4 kbytes)
E7 or E8 control
program area
(4 kbytes)
(1-kbyte work area
for flash memory
programming)
(1-kbyte work area
for flash memory
programming)
Note has been deleted.
Section 5 Clock Pulse
Generators
Figure 5.3 Typical
Connection to Crystal
Resonator
66
1
2
C
1
C
2
OSC
OSC
C = C = 10 to 22 pF
21
Figure 5.5 Typical
Connection to Ceramic
Resonator
66
OSC
1
OSC
2
C
1
C
2
C
1
= 5 to 30 pF
C
2
= 5 to 30 pF
Section 7 ROM 79 The features of the 20-kbyte (4 kbytes of them are the E7 or
E8 control program area) flash memory built into HD64F3672
are summarized below.
Table 7.2 Boot Mode
Operation
85
H'00
H'55
Transmits data H'55 when data H'00
is received error-free.
• Calculates bit rate and
• Transmits data H'00 to
end indication.
Bit rate adjustment
H'55 reception.