Datasheet

Appendix
Rev.4.00 Nov. 02, 2005 Page 264 of 304
REJ09B0143-0400
Table A.3 Number of Cycles in Each Instruction
Execution Status
Access Location
(Instruction Cycle) On-Chip Memory On-Chip Peripheral Module
Instruction fetch S
I
2 —
Branch address read S
J
Stack operation S
K
Byte data access S
L
2 or 3*
Word data access S
M
—
Internal operation S
N
1
Note: * Depends on which on-chip peripheral module is accessed. See section 16.1, Register
Addresses (Address Order).