Datasheet

Section 1 Overview
Rev.4.00 Nov. 02, 2005 Page 2 of 304
REJ09B0143-0400
1.2 Internal Block Diagram
P17/IRQ3/TRGV
P16
P15
P14/IRQ0
P12
P11
P10
P57
P56
P55/WKP5/ADTRG
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0
V
CL
V
SS
V
CC
RES TEST NMI
AV
CC
P22/TXD
P21/RXD
P20/SCK3
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
P76/TMOV
P75/TMCIV
P74/TMRIV
E10T_0*
E10T_1*
E10T_2*
OSC1 OSC2
Port 1
Data bus (upper)
CPU
H8/300H
ROM
RAM
Data bus (lower)
Timer W
SCI3
Watchdog
timer
Timer V
A/D converter
Port B
CMOS large current port I
OL
= 20 mA @ V
OL
= 1.5 V
System
clock
generator
Port 2Port 5
Address bus
Port 7Port 8
Note: * Can also be used for the E7 or E8 emulator.
Figure 1.1 Internal Block Diagram