Datasheet

Rev.4.00 Nov. 02, 2005 Page xxiii of xxiv
Tables
Section 1 Overview
Table 1.1
Pin Functions ............................................................................................................ 5
Section 2 CPU
Table 2.1 Operation Notation ................................................................................................. 16
Table 2.2 Data Transfer Instructions.......................................................................................17
Table 2.3 Arithmetic Operations Instructions (1) ...................................................................18
Table 2.3 Arithmetic Operations Instructions (2) ...................................................................19
Table 2.4 Logic Operations Instructions.................................................................................20
Table 2.5 Shift Instructions..................................................................................................... 20
Table 2.6 Bit Manipulation Instructions (1)............................................................................ 21
Table 2.6 Bit Manipulation Instructions (2)............................................................................ 22
Table 2.7 Branch Instructions ................................................................................................. 23
Table 2.8 System Control Instructions.................................................................................... 24
Table 2.9 Block Data Transfer Instructions ............................................................................ 25
Table 2.10 Addressing Modes .................................................................................................. 27
Table 2.11 Absolute Address Access Ranges........................................................................... 29
Table 2.12 Effective Address Calculation (1)........................................................................... 30
Table 2.12 Effective Address Calculation (2)........................................................................... 31
Section 3 Exception Handling
Table 3.1
Exception Sources and Vector Address .................................................................. 42
Table 3.2 Interrupt Wait States ............................................................................................... 51
Section 4 Address Break
Table 4.1
Access and Data Bus Used ..................................................................................... 57
Section 5 Clock Pulse Generators
Table 5.1 Crystal Resonator Parameters ................................................................................. 66
Section 6 Power-Down Modes
Table 6.1 Operating Frequency and Waiting Time.................................................................71
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 75
Table 6.3 Internal State in Each Operating Mode................................................................... 75
Section 7 ROM
Table 7.1
Setting Programming Modes .................................................................................. 83
Table 7.2 Boot Mode Operation ............................................................................................. 85
Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible................................................................................................................... 86
Table 7.4 Reprogram Data Computation Table ...................................................................... 89