Datasheet

Section 16 List of Registers
Rev.4.00 Nov. 02, 2005 Page 218 of 304
REJ09B0143-0400
16.1 Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Abbre-
viation Bit No Address
Module
Name
Data Bus
Width
Access
State
Timer mode register W TMRW 8 H'FF80 Timer W 8 2
Timer control register W TCRW 8 H'FF81 Timer W 8 2
Timer interrupt enable register W TIERW 8 H'FF82 Timer W 8 2
Timer status register W TSRW 8 H'FF83 Timer W 8 2
Timer I/O control register 0 TIOR0 8 H'FF84 Timer W 8 2
Timer I/O control register 1 TIOR1 8 H'FF85 Timer W 8 2
Timer counter TCNT 16 H'FF86 Timer W 16*
1
2
General register A GRA 16 H'FF88 Timer W 16*
1
2
General register B GRB 16 H'FF8A Timer W 16*
1
2
General register C GRC 16 H'FF8C Timer W 16*
1
2
General register D GRD 16 H'FF8E Timer W 16*
1
2
Flash memory control register 1 FLMCR1 8 H'FF90 ROM 8 2
Flash memory control register 2 FLMCR2 8 H'FF91 ROM 8 2
Erase block register 1 EBR1 8 H'FF93 ROM 8 2
Flash memory enable register FENR 8 H'FF9B ROM 8 2
Timer control register V0 TCRV0 8 H'FFA0 Timer V 8 3
Timer control/status register V TCSRV 8 H'FFA1 Timer V 8 3
Timer constant register A TCORA 8 H'FFA2 Timer V 8 3
Timer constant register B TCORB 8 H'FFA3 Timer V 8 3
Timer counter V TCNTV 8 H'FFA4 Timer V 8 3
Timer control register V1 TCRV1 8 H'FFA5 Timer V 8 3
Serial mode register SMR 8 H'FFA8 SCI3 8 3
Bit rate register BRR 8 H'FFA9 SCI3 8 3
Serial control register 3 SCR3 8 H'FFAA SCI3 8 3