Datasheet

Section 14 A/D Converter
Rev.4.00 Nov. 02, 2005 Page 211 of 304
REJ09B0143-0400
Table 14.3 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol Min Typ Max Min Typ Max
A/D conversion start delay t
D
6 — 9 4 — 5
Input sampling time t
SPL
— 31 — — 15 —
A/D conversion time t
CONV
131 — 134 69 — 70
Note: All values represent the number of states.
14.4.4 External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit is set to 1 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input
pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single
and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 14.3
shows the timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 14.3 External Trigger Input Timing