Datasheet

Section 14 A/D Converter
Rev.4.00 Nov. 02, 2005 Page 210 of 304
REJ09B0143-0400
14.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
D
) has passed after the ADST bit is set to 1, then
starts conversion. Figure 14.2 shows the A/D conversion timing. Table 14.3 shows the A/D
conversion time.
As indicated in figure 14.2, the A/D conversion time includes t
D
and the input sampling time. The
length of t
D
varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 14.3.
In scan mode, the values given in table 14.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
(1)
(2)
t
D
t
SPL
t
CONV
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1) : ADCSR write cycle
(2) : ADCSR address
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 14.2 A/D Conversion Timing