Datasheet

Section 14 A/D Converter
Rev.4.00 Nov. 02, 2005 Page 208 of 304
REJ09B0143-0400
Bit Bit Name Initial Value R/W Description
2
1
0
CH2
CH1
CH0
0
0
0
R/W
R/W
R/W
Channel Select 0 to 2
Select analog input channels.
When SCAN = 0 When SCAN = 1
X00: AN0 X00: AN0
X01: AN1 X01: AN0 to AN1
X10: AN2 X10: AN0 to AN2
X11: AN3 X11: AN0 to AN3
Legend: X: Don't care.
14.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit Bit Name Initial Value R/W Description
7 TRGE 0 R/W Trigger Enable
A/D conversion is started at the falling edge and the
rising edge of the external trigger signal (ADTRG)
when this bit is set to 1.
The selection between the falling edge and rising
edge of the external trigger pin (ADTRG) conforms
to the WPEG5 bit in the interrupt edge select
register 2 (IEGR2)
6 to 1 — All 1 — Reserved
These bits are always read as 1.
0 — 0 R/W Reserved
Do not set this bit to 1, though the bit is
readable/writable.