Datasheet

Rev.4.00 Nov. 02, 2005 Page xx of xxiv
Figure 13.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 180
Figure 13.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 181
Figure 13.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)...................... 183
Figure 13.8 Sample Serial Reception Data Flowchart (2) .......................................................... 184
Figure 13.9 Data Format in Clocked Synchronous Communication .......................................... 185
Figure 13.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode...... 187
Figure 13.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 188
Figure 13.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode............... 189
Figure 13.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 190
Figure 13.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)............................................................................... 192
Figure 13.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 194
Figure 13.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 195
Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 197
Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 198
Figure 13.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 199
Figure 13.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 202
Section 14 A/D Converter
Figure 14.1 Block Diagram of A/D Converter ........................................................................... 204
Figure 14.2 A/D Conversion Timing.......................................................................................... 210
Figure 14.3 External Trigger Input Timing ................................................................................ 211
Figure 14.4 A/D Conversion Accuracy Definitions (1).............................................................. 213
Figure 14.5 A/D Conversion Accuracy Definitions (2).............................................................. 213
Figure 14.6 Analog Input Circuit Example ................................................................................ 214
Section 15 Power Supply Circuit
Figure 15.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 215
Figure 15.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 216
Section 17 Electrical Characteristics
Figure 17.1 System Clock Input Timing .................................................................................... 242
Figure 17.2 RES Low Width Timing.......................................................................................... 242
Figure 17.3 Input Timing............................................................................................................ 242
Figure 17.4 SCK3 Input Clock Timing ...................................................................................... 243
Figure 17.5 SCI3 Input/Output Timing in Clocked Synchronous Mode .................................... 243
Figure 17.6 Output Load Circuit ................................................................................................ 244