Datasheet

Section 13 Serial Communication Interface 3 (SCI3)
Rev.4.00 Nov. 02, 2005 Page 177 of 304
REJ09B0143-0400
13.4 Operation in Asynchronous Mode
Figure 13.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units,
enabling full duplex. Both the transmitter and the receiver also have a double-buffered structure,
so data can be read or written during transmission or reception, enabling continuous data transfer.
LSB
Start
bit
MSB
Mark state
Stop bit
Transmit/receive data
1
Serial
data
Parity
bit
1 bit 1 or
2 bits
7 or 8 bits
1 bit,
or none
One unit of transfer data (character or frame)
Figure 13.2 Data Format in Asynchronous Communication
13.4.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3’s serial clock source, according to the setting of the
COM bit in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the
SCK3 pin, the clock frequency should be 16 times the bit rate used.
When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 13.3.
0
1 character (frame)
D0 D1 D2 D3 D4 D5 D6 D7 0/1
11
Clock
Serial data
Figure 13.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)