Datasheet

Rev.4.00 Nov. 02, 2005 Page xvii of xxiv
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ................................................................................................. 2
Figure 1.2 Pin Arrangement (FP-64E)............................................................................................ 3
Figure 1.3 Pin Arrangement (FP-48F, FP-48B).............................................................................. 4
Section 2 CPU
Figure 2.1 Memory Map.................................................................................................................8
Figure 2.2 CPU Registers ...............................................................................................................9
Figure 2.3 Usage of General Registers .........................................................................................10
Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 11
Figure 2.5 General Register Data Formats (1)..............................................................................13
Figure 2.5 General Register Data Formats (2)..............................................................................14
Figure 2.6 Memory Data Formats.................................................................................................15
Figure 2.7 Instruction Formats......................................................................................................26
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 30
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 32
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 33
Figure 2.11 CPU Operation States................................................................................................ 34
Figure 2.12 State Transitions........................................................................................................ 35
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to
Same Address............................................................................................................ 36
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 49
Figure 3.2 Stack Status after Exception Handling ........................................................................ 51
Figure 3.3 Interrupt Sequence.......................................................................................................52
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 53
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 55
Figure 4.2 Address Break Interrupt Operation Example (1).........................................................59
Figure 4.2 Address Break Interrupt Operation Example (2).........................................................60
Figure 4.3 Operation when Condition is not Satisfied in Branch Instruction ............................... 61
Figure 4.4 Operation when Another Interrupt is Accepted at Address Break
Setting Instruction ....................................................................................................... 62
Figure 4.5 Operation when the Instruction Set is not Executed and does not
Branch due to Conditions not Being Satisfied............................................................. 63