Datasheet

Section 11 Timer W
Rev.4.00 Nov. 02, 2005 Page 155 of 304
REJ09B0143-0400
11.5.7 Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure
11.22 shows the timing of the IMFA to IMFD flag setting at input capture.
GRA to GRD
TCNT
Input capture
signal
φ
N
N
IMFA to IMFD
IRRTW
Figure 11.22 Timing of IMFA to IMFD Flag Setting at Input Capture
11.5.8 Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 11.23 shows the status flag clearing timing.
IMFA to IMFD
Write signal
Address
φ
TSRW address
IRRTW
TSRW write cycle
T1 T2
Figure 11.23 Timing of Status Flag Clearing by CPU