Datasheet

Section 11 Timer W
Rev.4.00 Nov. 02, 2005 Page 152 of 304
REJ09B0143-0400
Figure 11.16 shows the output compare timing.
GRA to GRD
TCNT
TCNT input
clock
φ
N
N
N+1
Compare
match signal
FTIOA to FTIOD
Figure 11.16 Output Compare Output Timing
11.5.3 Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR0 and TIOR1. Figure 11.17 shows the timing when the falling edge is selected. The pulse
width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will
not be detected correctly.
TCNT
Input capture
input
φ
N–1 N N+1 N+2
N
GRA to GRD
Input capture
signal
Figure 11.17 Input Capture Input Signal Timing