Datasheet

Section 11 Timer W

Rev.4.00 Nov. 02, 2005 Page 146 of 304

REJ09B0143-0400

TCNT value

H'DA91

H'0245

H'0000

GRC

Time

H'0245

FTIOA

GRA

H'5480H'0245

H'FFFF

H'5480

H'DA91

Figure 11.8 Buffer Operation Example (Input Capture)

11.4.2 PWM Operation

In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB,

GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and

FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register

functions as an output compare register automatically. The output level of each pin depends on the

corresponding timer output level set bit (TOB, TOC, and TOD) in TCRW. When TOB is 1, the

FTIOB output goes to 1 at compare match A and to 0 at compare match B. When TOB is 0, the

FTIOB output goes to 0 at compare match A and to 1 at compare match B. Thus the compare

match output level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode.

If the same value is set in the cycle register and the duty register, the output does not change when

a compare match occurs.

Figure 11.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT

is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB,

TOC, and TOD = 1: initial output values are set to 1).