Datasheet
Section 11 Timer W
Rev.4.00 Nov. 02, 2005 Page 137 of 304
REJ09B0143-0400
11.3.3 Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Bit Bit Name Initial Value R/W Description
7 OVIE 0 R/W Timer Overflow Interrupt Enable
When this bit is set to 1, FOVI interrupt requested by OVF
flag in TSRW is enabled.
6
5
4
1
1
1
Reserved
These bits are always read as 1.
3 IMIED 0 R/W Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, IMID interrupt requested by IMFD
flag in TSRW is enabled.
2 IMIEC 0 R/W Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, IMIC interrupt requested by IMFC
flag in TSRW is enabled.
1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, IMIB interrupt requested by IMFB
flag in TSRW is enabled.
0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, IMIA interrupt requested by IMFA
flag in TSRW is enabled.
11.3.4 Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Bit Bit Name Initial Value R/W Description
7 OVF 0 R/W Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FFFF to H'0000
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
6
5
4
1
1
1
Reserved
These bits are always read as 1.