Datasheet

Rev.4.00 Nov. 02, 2005 Page x of xxiv
3.2.5 Wakeup Interrupt Flag Register (IWPR)................................................................ 47
3.3 Reset Exception Handling.................................................................................................... 48
3.4 Interrupt Exception Handling .............................................................................................. 48
3.4.1 External Interrupts .................................................................................................. 48
3.4.2 Internal Interrupts ................................................................................................... 49
3.4.3 Interrupt Handling Sequence .................................................................................. 50
3.4.4 Interrupt Response Time......................................................................................... 51
3.5 Usage Notes......................................................................................................................... 53
3.5.1 Interrupts after Reset............................................................................................... 53
3.5.2 Notes on Stack Area Use ........................................................................................ 53
3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 53
Section 4 Address Break .....................................................................................55
4.1 Register Descriptions...........................................................................................................55
4.1.1 Address Break Control Register (ABRKCR) ......................................................... 56
4.1.2 Address Break Status Register (ABRKSR) ............................................................ 57
4.1.3 Break Address Registers (BARH, BARL).............................................................. 58
4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 58
4.2 Operation ............................................................................................................................. 59
4.3 Usage Notes......................................................................................................................... 61
Section 5 Clock Pulse Generators .......................................................................65
5.1 System Clock Generator ...................................................................................................... 65
5.1.1 Connecting Crystal Resonator ................................................................................ 66
5.1.2 Connecting Ceramic Resonator .............................................................................. 66
5.1.3 External Clock Input Method ................................................................................. 67
5.2 Prescalers............................................................................................................................. 67
5.2.1 Prescaler S .............................................................................................................. 67
5.3 Usage Notes......................................................................................................................... 67
5.3.1 Note on Resonators................................................................................................. 67
5.3.2 Notes on Board Design........................................................................................... 68
Section 6 Power-Down Modes............................................................................69
6.1 Register Descriptions...........................................................................................................70
6.1.1 System Control Register 1 (SYSCR1).................................................................... 70
6.1.2 System Control Register 2 (SYSCR2).................................................................... 72
6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 73
6.2 Mode Transitions and States of LSI..................................................................................... 74
6.2.1 Sleep Mode............................................................................................................. 76
6.2.2 Standby Mode......................................................................................................... 76