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To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas

Electronics Corporation took over all the business of both

companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

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Summary of content (334 pages)

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To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3672 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/3672F H8/3670F HD64F3672 HD64F3670 Rev.4.00 2005.
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Rev.4.00 Nov.
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
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Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
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Preface The H8/3672 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/3672 Group in the design of application systems.
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5. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode). Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8/3672 Group manuals: Document Title Document No. H8/3672 Group Hardware Manual This manual H8/300H Series Software Manual REJ09B0213 User's manuals for development tools: Document Title Document No.
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Rev.4.00 Nov.
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Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 2 Pin Arrangement ..................................................................................
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3.3 3.4 3.5 3.2.5 Wakeup Interrupt Flag Register (IWPR) ................................................................ 47 Reset Exception Handling.................................................................................................... 48 Interrupt Exception Handling .............................................................................................. 48 3.4.1 External Interrupts .................................................................................................. 48 3.
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6.3 6.4 6.5 6.2.3 Subsleep Mode........................................................................................................ 76 Operating Frequency in Active Mode.................................................................................. 77 Direct Transition .................................................................................................................. 77 Module Standby Function.............................................................................................
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9.4 9.5 9.6 9.3.3 Port Data Register 5 (PDR5) ................................................................................ 104 9.3.4 Port Pull-Up Control Register 5 (PUCR5)............................................................ 105 9.3.5 Pin Functions ........................................................................................................ 105 Port 7..................................................................................................................................
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11.3.7 Timer Counter (TCNT)......................................................................................... 141 11.3.8 General Registers A to D (GRA to GRD)............................................................. 141 11.4 Operation ........................................................................................................................... 142 11.4.1 Normal Operation ................................................................................................. 142 11.4.
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13.5 13.6 13.7 13.8 13.4.4 Serial Data Reception ........................................................................................... 181 Operation in Clocked Synchronous Mode ......................................................................... 185 13.5.1 Clock..................................................................................................................... 185 13.5.2 SCI3 Initialization........................................................................................
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Section 16 List of Registers ...............................................................................217 16.1 Register Addresses (Address Order).................................................................................. 218 16.2 Register Bits....................................................................................................................... 221 16.3 Register States in Each Operating Mode ...........................................................................
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Rev.4.00 Nov.
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Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Overview Internal Block Diagram ................................................................................................. 2 Pin Arrangement (FP-64E)............................................................................................ 3 Pin Arrangement (FP-48F, FP-48B).............................................................................. 4 Section 2 CPU Figure 2.1 Memory Map............................................................
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Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Clock Pulse Generators Block Diagram of Clock Pulse Generators.................................................................. 65 Block Diagram of System Clock Generator ................................................................ 65 Typical Connection to Crystal Resonator.................................................................... 66 Equivalent Circuit of Crystal Resonator..................................
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Figure 11.2 Free-Running Counter Operation ............................................................................ 142 Figure 11.3 Periodic Counter Operation..................................................................................... 143 Figure 11.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 143 Figure 11.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 144 Figure 11.
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Figure 13.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 180 Figure 13.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 181 Figure 13.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)...................... 183 Figure 13.8 Sample Serial Reception Data Flowchart (2) ..........................................................
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Appendix B I/O Port Block Diagrams Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 276 Figure B.2 Port 1 Block Diagram (P14) ..................................................................................... 277 Figure B.3 Port 1 Block Diagram (P16, P15, P12, P10)............................................................. 278 Figure B.4 Port 1 Block Diagram (P11) .................................................................
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Rev.4.00 Nov.
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Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 16 Table 2.2 Data Transfer Instructions....................................................................................... 17 Table 2.3 Arithmetic Operations Instructions (1) ...............................
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Table 7.5 Table 7.6 Additional-Program Data Computation Table ........................................................ 89 Programming Time ................................................................................................. 89 Section 10 Timer V Table 10.1 Pin Configuration.................................................................................................. 117 Table 10.2 Clock Signals to Input to TCNTV and Counting Conditions ...............................
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Section 1 Overview Section 1 Overview 1.
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Section 1 Overview OSC1 OSC2 RAM Timer W SCI3 P76/TMOV P75/TMCIV P74/TMRIV P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI Watchdog timer Timer V A/D converter Port 5 P57 P56 P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 AVCC PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Port B Note: * Can also be used for the E7 or E8 emulator. Figure 1.1 Internal Block Diagram Rev.4.00 Nov. 02, 2005 Page 2 of 304 REJ09B0143-0400 CMOS large current port IOL = 20 mA @ VOL = 1.
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Section 1 Overview NC NC NMI P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD E10T_0* E10T_1* E10T_2* P20/SCK3 P21/RXD P22/TXD NC NC Pin Arrangement 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC 49 32 NC NC 50 31 NC P14/IRQ0 51 30 P76/TMOV P15 52 29 P75/TMCIV P16 53 28 P74/TMRIV P17/IRQ3/TRGV 54 27 P57 NC 55 26 P56 NC 56 25 P12 NC 57 24 P11 NC 58 23 P10 PB3/AN3 59 22 P55/WKP5/ADTRG PB2/AN2 60 21 P54/WKP4 PB1/AN1 61 20 P53/WKP3 PB0/AN
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NMI P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD E10T_0* E10T_1* E10T_2* P20/SCK3 P21/RXD P22/TXD Section 1 Overview 36 35 34 33 32 31 30 29 28 27 26 25 P14/IRQ0 37 24 P76/TMOV P15 38 23 P75/TMCIV P16 39 22 P74/TMRIV P17/IRQ3/TRGV 40 21 P57 NC 41 20 P56 NC 42 19 P12 NC 43 18 P11 NC 44 17 P10 PB3/AN3 45 16 P55/WKP5/ADTRG PB2/AN2 46 15 P54/WKP4 PB1/AN1 47 14 P53/WKP3 PB0/AN0 48 13 P52/WKP2 H8/3672 4 5 6 7 8 9 10 11 12 NC NC VCL RES TE
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Section 1 Overview 1.4 Pin Functions Table 1.1 Pin Functions Pin No. Type Symbol FP-64E FP-48F, FP-48B I/O Functions Power source pins VCC 12 10 Input Power supply pin. Connect this pin to the system power supply. VSS 9 7 Input Ground pin. Connect this pin to the system power supply (0V). AVCC 3 1 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply.
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Section 1 Overview Pin No. Type Symbol FP-64E FP-48F, FP-48B I/O Functions Timer V TMOV 30 24 Output This is an output pin for waveforms generated by the output compare function. TMCIV 29 23 Input External event input pin. TMRIV 28 22 Input Counter reset input pin. TRGV 54 40 Input Counter start trigger input pin. FTCI 36 26 Input External event input pin.
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Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs  Can execute H8/300 CPUs object programs  Additional eight 16-bit extended registers  32-bit transfer and arithmetic and logic instructions are added  Signed multiply and divide instructions are added.
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Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figure 2.1 shows the memory map.
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Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR).
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Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
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Section 2 CPU Free area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
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Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
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Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
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Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data LSB 0 LSB ERn 31 16 15 MSB [Legend] ERn : General register ER En : General register E Rn : General register R RnH : General register RH RnL : General register RL MSB : Most significant bit LSB 0 : Least significant bit Figure 2.5 General Register Data Formats (2) Rev.4.00 Nov.
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Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
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Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.
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Section 2 CPU Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) → Rd, Cannot be used in this LSI. MOVTPE B Rs → (EAs) Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
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Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
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Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
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Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
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Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
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Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd), EXR → (EAd) Transfers the CCR contents to a destination location.
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Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5 + → @ER6 +, R4L – 1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5 + → @ER6 +, R4 – 1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.4.
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Section 2 CPU • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. • Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
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Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.
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Section 2 CPU Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand.
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Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address Access Range 8 bits (@aa:8) H'FF00 to H'FFFF 16 bits (@aa:16) H'0000 to H'FFFF 24 bits (@aa:24) H'0000 to H'FFFF Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly.
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Section 2 CPU Specified by @aa:8 Dummy Branch address Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.
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Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
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Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states.
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Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 16.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size.
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Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode. In the program halt state there are a sleep mode, and standby mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes.
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Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
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Section 2 CPU Bit manipulation for two registers assigned to the same address Example: Bit manipulation for the timer load register and timer counter (Applicable for timer B and timer C, not for the series of this LSI.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address.
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Section 2 CPU • Prior to executing BSET instruction P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 • BSET instruction executed instruction BSET #0, @PDR5 The BSET instruction is executed for port 5.
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Section 2 CPU • Prior to executing BSET instruction MOV.B MOV.B MOV.B #80, R0L, R0L, R0L @RAM0 @PDR5 The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5.
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Section 2 CPU Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin.
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Section 2 CPU • Prior to executing BCLR instruction MOV.B MOV.B MOV.B #3F, R0L, R0L, R0L @RAM0 @PCR5 The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5.
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Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.
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Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.
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Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. • • • • • Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt flag register 1 (IRR1) Wakeup interrupt flag register (IWPR) 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of pins and IRQ3 and IRQ0.
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Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Bit Bit Name Initial Value R/W Description 7  1  Reserved 6  1  These bits are always read as 1.
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Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, and external pin interrupts. Bit Bit Name Initial Value R/W Description 7 IENDT 0 R/W Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6  0  Reserved This bit is always read as 0. 5 IENWP 0 R/W Wakeup Interrupt Enable This bit is an enable bit, which is common to the pins WKP5 to WKP0.
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Section 3 Exception Handling 3.2.4 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests. Bit Bit Name Initial Value R/W Description 7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag [Setting condition] When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1.
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Section 3 Exception Handling 3.2.5 Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests. Bit Bit Name Initial Value R/W Description 7 6 5   IWPF5 1 1 0   R/W 4 IWPF4 0 R/W 3 IWPF3 0 R/W 2 IWPF2 0 R/W 1 IWPF1 0 R/W 0 IWPF0 0 R/W Reserved These bits are always read as 1. WKP5 Interrupt Request Flag [Setting condition] When WKP5 pin is designated for interrupt input and the designated signal edge is detected.
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Section 3 Exception Handling 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock cycles.
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Section 3 Exception Handling WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2.
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Section 3 Exception Handling When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.4.3 Interrupt Handling Sequence Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1.
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Section 3 Exception Handling SP – 4 SP (R7) CCR SP – 3 SP + 1 CCR*3 SP – 2 SP + 2 PCH SP – 1 SP + 3 PCL SP (R7) SP + 4 Even address Stack area Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling [Legend] PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1.
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REJ09B0143-0400 Rev.4.00 Nov. 02, 2005 Page 52 of 304 Figure 3.3 Interrupt Sequence (2) (1) (4) Instruction prefetch (3) Internal processing (5) (1) Stack access (6) (7) (9) Vector fetch (8) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.
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Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
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Section 3 Exception Handling Rev.4.00 Nov.
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Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
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Section 4 Address Break 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Bit Bit Name Initial Value R/W Description 7 RTINTE 1 R/W RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked. 6 CSEL1 0 R/W Condition Select 1 and 0 5 CSEL0 0 R/W These bits set address break conditions.
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Section 4 Address Break When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 16.1, Register Addresses (Address Order). Table 4.
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Section 4 Address Break 4.1.3 Break Address Registers (BARH, BARL) BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF. 4.1.4 Break Data Registers (BDRH, BDRL) BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break interrupt.
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Section 4 Address Break 4.2 Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked because of the I bit in CCR of the CPU. Figures 4.
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Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked.
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Section 4 Address Break 4.3 Usage Notes When an address break is set to an instruction after a conditional branch instruction, and the instruction set when the condition of the branch instruction is not satisfied is executed (see figure 4.3), note that an address break interrupt request is not generated. Therefore an address break must not be set to the instruction after a conditional branch instruction. [Register setting] [Program] ABRKCR=H'80 BAR=H'0136 012A MOV.B . . .
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Section 4 Address Break [Register setting] ABRKCR=H'80 BAR=H'0144 External interrupt MOV [Program] 001C : 0142 * 0144 0146 0900 : MOV.B #H'23,R1H MOV.B #H'45,R1H MOV.B #H'67,R1H MOV MOV instruction instruction instruction Internal prefetch prefetch prefetch processing Address bus 0142 0144 0146 Underlined indicates the address to be stacked.
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Section 4 Address Break [Register setting] • ADBRKCR = H'80 • BAR = H'0150 [Program] 0134 BNE 0136 NOP 0138 NOP * 0150 MOV.B . . . BNE NOP MOV NOP instruction instruction instruction instruction prefetch prefetch prefetch prefetch φ Address bus 0134 0136 0150 0138 Address break interrupt request Interrupt acceptance Figure 4.5 Operation when the Instruction Set is not Executed and does not Branch due to Conditions not Being Satisfied Rev.4.00 Nov.
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Section 4 Address Break Rev.4.00 Nov.
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Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including a system clock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. Figure 5.1 shows a block diagram of the clock pulse generators.
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Section 5 Clock Pulse Generators 5.1.1 Connecting Crystal Resonator Figure 5.3 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. Figure 5.4 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 5.1 should be used. C1 OSC 1 OSC 2 C2 C1 = C 2 = 10 to 22 pF Figure 5.3 Typical Connection to Crystal Resonator LS RS CS OSC 1 OSC 2 C0 Figure 5.
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Section 5 Clock Pulse Generators 5.1.3 External Clock Input Method Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.6 shows a typical connection. The duty cycle of the external clock signal must be 45 to 55%. OSC1 OSC 2 External clock input Open Figure 5.6 Example of External Clock Input 5.2 Prescalers 5.2.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once per clock period.
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Section 5 Clock Pulse Generators 5.3.2 Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.7). Signal A Avoid Signal B C1 OSC1 C2 OSC2 Figure 5.7 Example of Incorrect Board Design Rev.4.00 Nov.
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Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has five modes of operation after a reset. These include a normal active mode and three power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. • Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
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Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. • System control register 1 (SYSCR1) • System control register 2 (SYSCR2) • Module standby control register 1 (MSTCR1) 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Bit Bit Name Initial Value R/W Description 7 SSBY 0 Software Standby R/W This bit selects the mode to transit after the execution of the SLEEP instruction.
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Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 0 0 1 1 0 1 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 0 8,192 states 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 states 1.0 1.6 2.0 4.1 8.2 16.4 32.8 0 32,768 states 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65,536 states 4.1 6.6 8.2 16.4 32.8 65.5 131.1 0 131,072 states 8.2 13.1 16.4 32.8 65.5 131.1 262.1 1 1,024 states 0.06 0.10 0.13 0.26 0.51 1.
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Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value R/W Description 7 SMSEL 0 R/W Sleep Mode Selection This bit selects the mode to transit after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2. 6  0  Reserved This bit is always read as 0.
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Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W Description 7  0  Reserved 6  0  These bits are always read as 0.
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Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. A direct transition from active mode to active mode changes the operating frequency.
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Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling DTON SSBY SMSEL Transition Mode after SLEEP Transition Mode due to Instruction Execution Interrupt 0 0 0 Sleep mode Active mode 0 1 Subsleep mode Active mode 1 X Standby mode Active mode X 0* Active mode (direct transition) — 1 Legend: * Table 6.3 X: Don’t care.
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Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register.
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Section 6 Power-Down Modes 6.3 Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2 to MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. 6.4 Direct Transition The CPU can execute programs in active mode. The operating frequency can be changed by making a transition directly from active mode to active mode.
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Section 6 Power-Down Modes Rev.4.00 Nov.
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Section 7 ROM Section 7 ROM The features of the 20-kbyte (4 kbytes of them are the E7 or E8 control program area) flash memory built into HD64F3672 are summarized below. • Programming/erase methods  The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 kbyte × 4 blocks, 16 kbytes × 1 block. To erase the entire flash memory, each block must be erased in turn.
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Section 7 ROM Erase unit H'0000 H'0001 H'0002 H'0080 H'0081 H'0082 H'0380 H'0381 H'0382 H'0400 H'0401 H'0402 H'0480 H'0481 H'0481 H'0780 H'0781 H'0782 H'0800 H'0801 H'0802 H'0880 H'0881 H'0882 H'0B80 H'0B81 H'0B82 H'0C00 H'0C01 H'0C02 H'0C80 H'0C81 H'0C82 H'0F80 H'0F81 H'0F82 H'1000 H'1001 H'1002 H'1080 H'1081 H'1082 H'10FF H'4F80 H'4F81 H'4F82 H'4FFF Programming unit: 128 bytes H'007F H'00FF 1kbyte Erase unit H'03FF Programming unit: 128 bytes H'047F H'
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Section 7 ROM 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing. Bit Bit Name Initial Value R/W 7 — — 0 Description Reserved This bit is always read as 0. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled.
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Section 7 ROM 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit Bit Name Initial Value R/W 7 FLER 0 R Description Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. See 7.5.3, Error Protection, for details.
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Section 7 ROM 7.2.4 Flash Memory Enable Register (FENR) Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, and EBR1. Bit Bit Name Initial Value R/W Description 7 FLSHE R/W Flash Memory Control Register Enable 0 Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 — All 0 — Reserved These bits are always read as 0. 7.
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Section 7 ROM 7.3.1 Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3.
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Section 7 ROM Boot Mode Operation Host Operation Communication Contents Processing Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free.
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Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 MHz 9,600 bps 8 to 16 MHz 4,800 bps 4 to 16 MHz 2,400 bps 2 to 16 MHz 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program.
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Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
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Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
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Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 — 1 1 1 Remains in erased state Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Additional-Program Data Comments 0 0 0 Additional-program bit 0 1 1 No additional programming 1 0 1 No additional programming 1 1 1 No additional programming Comments Table 7.
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Section 7 ROM 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.
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Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 10 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs * n←n+1 Read verify data No Verify data + all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erase block erased ? n ≤100 ? Yes Yes Yes No SWE bit ← 0 SWE b
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Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subsleep mode or standby mode.
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Section 8 RAM Section 8 RAM This LSI has 2 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Note: The address area H'F780 to H'FB7F must not be accessed while the E7 or E8 is being in use. RAM0400A_000020020300 Rev.4.00 Nov.
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Section 8 RAM Rev.4.00 Nov.
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Section 9 I/O Ports Section 9 I/O Ports The group of this LSI has twenty-six general I/O ports and four general input-only ports. Port 8 is a large current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings.
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Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description 7 IRQ3 0 P17/IRQ3/TRGV Pin Function Switch R/W This bit selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6  0  Reserved 5  0  These bits are always read as 0. 4 IRQ0 0 R/W P14/IRQ0 Pin Function Switch This bit selects whether pin P14/IRQ0 is used as P14 or as IRQ0.
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Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR14 0 W Bit 3 is a reserved bit.
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Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7 PUCR17 0 R/W 6 PUCR16 0 R/W 5 PUCR15 0 R/W Only bits for which PCR1 is cleared are valid. The pull-up MOS of P17 to P14 and P12 to P10 pins enter the onstate when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 4 PUCR14 0 R/W Bit 3 is a reserved bit.
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Section 9 I/O Ports P15 pin Register PCR1 Bit Name PCR15 Pin Function Setting value 0 P15 input pin 1 P15 output pin P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function 0 P14 input pin 1 P14 output pin X IRQ0 input pin Setting value 0 1 Legend: X: Don't care.
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Section 9 I/O Ports 9.2 Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses. P22/TXD Port 2 P21/RXD P20/SCK3 Figure 9.2 Port 2 Pin Configuration Port 2 has the following registers. • Port control register 2 (PCR2) • Port data register 2 (PDR2) 9.2.
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Section 9 I/O Ports 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Bit Bit Name Initial Value R/W 7  1  Reserved 6  1  These bits are always read as 1. 5  1  4  1  3  1  2 P22 0 R/W PDR2 stores output data for port 2 pins. 1 P21 0 R/W 0 P20 0 R/W If PDR2 is read while PCR2 bits are set to 1, the value stored in PDR2 is read.
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Section 9 I/O Ports P20/SCK3 pin Register SCR3 Bit Name CKE1 Setting Value 0 SMR PCR2 CKE0 COM PCR20 Pin Function 0 0 0 P20 input pin 1 P20 output pin 0 0 1 X SCK3 output pin 0 1 X X SCK3 output pin 1 X X X SCK3 input pin Legend: X: Don't care. 9.3 Port 5 Port 5 is a general I/O port also functioning as an A/D trigger input pin and wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3.
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Section 9 I/O Ports 9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W Description 7 POF7 0 R/W P57 Pin Function Switch 0: General I/O port 1: NMOS open-drain output 6 POF6 0 R/W P56 Pin Function Switch 0: General I/O port 1: NMOS open-drain output 5 WKP5 0 R/W P55/WKP5/ADTRG Pin Function Switch Selects whether pin P55/WKP5/ADTRG is used as P55 or as WKP5/ADTRG input.
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Section 9 I/O Ports 9.3.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W Description 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W When each of the port 5 pins P57 to P50 functions as an general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports 9.3.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7  0  Reserved 6  0  These bits are always read as 0. 5 PUCR55 0 R/W 4 PUCR54 0 R/W 3 PUCR53 0 R/W Only bits for which PCR5 is cleared are valid.
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Section 9 I/O Ports P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 0 P55 input pin 1 P55 output pin X WKP5/ADTRG input pin 1 Legend: X: Don't care. P54/WKP4 pin Register PMR5 PCR5 Bit Name WKP4 PCR54 Pin Function Setting Value 0 0 P54 input pin 1 P54 output pin X WKP4 input pin 1 Legend: X: Don't care.
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Section 9 I/O Ports P51/WKP1 pin Register PMR5 PCR5 Bit Name WKP1 PCR51 Pin Function Setting Value 0 0 P51 input pin 1 P51 output pin X WKP1 input pin 1 Legend: X: Don't care. P50/WKP0 pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Pin Function Setting Value 0 0 P50 input pin 1 P50 output pin X WKP0 input pin 1 Legend: X: Don't care. 9.4 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4.
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Section 9 I/O Ports 9.4.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Bit Bit Name Initial Value R/W Description 7    Reserved 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W Setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Note that the TCSRV setting of the timer V has priority for deciding input/output direction of the P76/TMOV pin.
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Section 9 I/O Ports 9.4.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P76/TMOV pin Register TCSRV PCR7 Bit Name OS3 to OS0 PCR76 Pin Function Setting Value 0000 0 P76 input pin 1 P76 output pin X TMOV output pin Other than the above values Legend: X: Don't care.
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Section 9 I/O Ports 9.5 Port 8 Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W has priority for functions of the pins P84/FTIOD, P83/FTIOC, P82/FTIOB, and P81/FTIOA. The P80/FTCI pin also functions as a timer W input port that is connected to the timer W regardless of the register setting of port 8. P84/FTIOD P83/FTIOC Port 8 P82/FTIOB P81/FTIOA P80/FTCI Figure 9.
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Section 9 I/O Ports 9.5.2 Port Data Register 8 (PDR8) PDR8 is a general I/O port data register of port 8. Bit Bit Name Initial Value R/W 7  0  6  0  5  0  4 P84 0 R/W PDR8 stores output data for port 8 pins. 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W If PDR8 is read while PCR8 bits are set to 1, the value stored in PDR8 is read. If PDR8 is read while PCR8 bits are cleared to 0, the pin states are read regardless of the value stored in PDR8. 0 P80 0 R/W 9.5.
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Section 9 I/O Ports P83/FTIOC pin Register TIOR1 PCR8 Bit Name IOC2 IOC1 IOC0 PCR83 Pin Function Setting Value 0 0 0 0 P83 input/FTIOC input pin 1 P83 output/FTIOC input pin 0 0 1 X FTIOC output pin 0 1 X X FTIOC output pin 1 X X 0 P83 input/FTIOC input pin 1 P83 output/FTIOC input pin Legend: X: Don't care.
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Section 9 I/O Ports P80/FTCI pin Register PCR8 Bit Name PCR80 Pin Function Setting Value 0 P80 input/FTCI input pin 1 P80 output/FTCI input pin 9.6 Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.6. PB3/AN3 Port B PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.6 Port B Pin Configuration Port B has the following register. • Port data register B (PDRB) Rev.4.00 Nov.
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Section 9 I/O Ports 9.6.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B. Bit Bit Name Initial Value R/W Description 7    Reserved 6    5    4    3 PB3  R The input value of each pin is read by reading this register. 2 PB2  R 1 PB1  R However, if a port B pin is designated as an analog input channel by ADCSR in A/D converter, 0 is read. 0 PB0  R Rev.4.00 Nov.
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Section 10 Timer V Section 10 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 10.1 shows a block diagram of timer V. 10.
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Section 10 Timer V TCRV1 TCORB Trigger control TRGV Comparator TCNTV Internal data bus Clock select TMCIV Comparator φ PSS TCORA TMRIV Clear control TCRV0 Interrupt request control TMOV [Legend] TCORA: TCORB: TCNTV: TCSRV: TCRV0: TCRV1: PSS: CMIA: CMIB: OVI: Output control TCSRV Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B
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Section 10 Timer V 10.2 Input/Output Pins Table 10.1 shows the timer V pin configuration. Table 10.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV Trigger input TRGV Input Trigger input to initiate counting 10.3 Register Descriptions Time V has the following registers.
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Section 10 Timer V 10.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle.
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Section 10 Timer V Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W These bits select clock signals to input to TCNTV and the counting condition in combination with ICKS0 in TCRV1. Refer to table 10.2. Table 10.
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Section 10 Timer V 10.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match.
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Section 10 Timer V OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match. 10.3.5 Timer Control Register V1 (TCRV1) TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. Bit Bit Name 7 to 5  Initial Value R/W All 1  Description Reserved These bits are always read as 1.
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Section 10 Timer V 10.4 Operation 10.4.1 Timer V Operation 1. According to table 10.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 10.2 shows the count timing with an internal clock signal selected, and figure 10.3 shows the count timing with both edges of an external clock signal selected. 2.
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Section 10 Timer V φ Internal clock TCNTV input clock TCNTV N–1 N N+1 Figure 10.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock TCNTV N–1 N N+1 Figure 10.3 Increment Timing with External Clock φ TCNTV H'FF H'00 Overflow signal OVF Figure 10.4 OVF Set Timing Rev.4.00 Nov.
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Section 10 Timer V φ TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 10.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin Figure 10.6 TMOV Output Timing φ Compare match A signal TCNTV N H'00 Figure 10.7 Clear Timing by Compare Match Rev.4.00 Nov.
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Section 10 Timer V φ TMRIV(External counter reset input pin ) TCNTV reset signal TCNTV N–1 N H'00 Figure 10.8 Clear Timing by TMRIV Input Rev.4.00 Nov.
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Section 10 Timer V 10.5 Timer V Application Examples 10.5.1 Pulse Output with Arbitrary Duty Cycle Figure 10.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 4.
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Section 10 Timer V 10.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 10.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3.
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Section 10 Timer V 10.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. 2. 3. 4. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 10.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence.
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Section 10 Timer V TCORA write cycle by CPU T2 T1 T3 φ Address TCORA address Internal write signal TCNTV N N+1 TCORA N M TCORA write data Compare match signal Inhibited Figure 10.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 10.13 Internal Clock Switching and TCNTV Operation Rev.4.00 Nov.
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Section 10 Timer V Rev.4.00 Nov.
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Section 11 Timer W Section 11 Timer W The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems. 11.
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Section 11 Timer W Table 11.
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Section 11 Timer W Internal clock: φ φ/2 φ/4 φ/8 External clock: FTCI FTIOA Clock selector FTIOB FTIOC Control logic FTIOD Comparator TIOR TSRW TIERW TCRW TMRW GRD GRC GRB Bus interface [Legend] TMRW: TCRW: TIERW: TSRW: TIOR: TCNT: GRA: GRB: GRC: GRD: IRRTW: GRA TCNT IRRTW Internal data bus Timer mode register W (8 bits) Timer control register W (8 bits) Timer interrupt enable register W (8 bits) Timer status register W (8 bits) Timer I/O control register (8 bits) Timer counter (16 bits
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Section 11 Timer W 11.2 Input/Output Pins Table 11.2 summarizes the timer W pins. Table 11.
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Section 11 Timer W 11.3.1 Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Bit Bit Name Initial Value R/W Description 7 CTS 0 Counter Start R/W The counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6  1  Reserved This bit is always read as 1. 5 BUFEB 0 R/W Buffer Operation B Selects the GRD function.
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Section 11 Timer W 11.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Bit Bit Name Initial Value R/W Description 7 CCLR R/W Counter Clear 0 The TCNT value is cleared by compare match A when this bit is 1. When it is 0, TCNT operates as a free-running counter. 6 CKS2 0 R/W Clock Select 2 to 0 5 CKS1 0 R/W Select the TCNT clock source.
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Section 11 Timer W 11.3.3 Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request. Bit Bit Name Initial Value R/W Description 7 OVIE 0 Timer Overflow Interrupt Enable R/W When this bit is set to 1, FOVI interrupt requested by OVF flag in TSRW is enabled. 6  1  Reserved 5  1  These bits are always read as 1.
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Section 11 Timer W Bit Bit Name Initial Value R/W Description 3 IMFD 0 Input Capture/Compare Match Flag D R/W [Setting conditions] • TCNT = GRD when GRD functions as an output compare register • The TCNT value is transferred to GRD by an input capture signal when GRD functions as an input capture register [Clearing condition] Read IMFD when IMFD = 1, then write 0 in IMFD 2 IMFC 0 R/W Input Capture/Compare Match Flag C [Setting conditions] • TCNT = GRC when GRC functions as an output compa
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Section 11 Timer W 11.3.5 Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Bit 7 Bit Name  Initial Value R/W 1  6 IOB2 0 R/W 5 4 IOB1 IOB0 0 0 R/W R/W 3  1  2 IOA2 0 R/W 1 0 IOA1 IOA0 0 0 R/W R/W Description Reserved This bit is always read as 1. I/O Control B2 Selects the GRB function.
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Section 11 Timer W 11.3.6 Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit 7 Bit Name Initial Value  1 R/W  6 IOD2 0 R/W 5 4 IOD1 IOD0 0 0 R/W R/W 3  1  2 IOC2 0 R/W 1 0 IOC1 IOC0 0 0 R/W R/W Legend: X: Don't care. Rev.4.00 Nov. 02, 2005 Page 140 of 304 REJ09B0143-0400 Description Reserved This bit is always read as 1. I/O Control D2 Selects the GRD function.
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Section 11 Timer W 11.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed.
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Section 11 Timer W 11.4 Operation The timer W has the following operating modes. • Normal Operation • PWM Operation 11.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE in TIERW is set to 1, an interrupt request is generated. Figure 11.
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Section 11 Timer W TCNT value GRA H'0000 Time CTS bit Flag cleared by software IMFA Figure 11.3 Periodic Counter Operation By setting a general register as an output compare register, compare match A, B, C, or D can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure 11.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output is selected for compare match A, and 0 output is selected for compare match B.
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Section 11 Timer W TCNT value H'FFFF GRA GRB Time H'0000 FTIOA Toggle output FTIOB Toggle output Figure 11.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 11.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B. TCNT value Counter cleared by compare match with GRA H'FFFF GRA GRB H'0000 Time FTIOA Toggle output FTIOB Toggle output Figure 11.
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Section 11 Timer W TCNT value H'FFFF H'F000 H'AA55 H'55AA H'1000 H'0000 Time FTIOA GRA H'1000 H'F000 H'55AA FTIOB GRB H'AA55 Figure 11.7 Input Capture Operating Example Figure 11.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal.
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Section 11 Timer W TCNT value H'FFFF H'DA91 H'5480 H'0245 H'0000 Time FTIOA GRA H'0245 GRC H'5480 H'DA91 H'0245 H'5480 Figure 11.8 Buffer Operation Example (Input Capture) 11.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output.
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Section 11 Timer W TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 11.9 PWM Mode Example (1) Figure 11.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0: initial output values are set to 1). TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 11.
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Section 11 Timer W Figure 11.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs.
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Section 11 Timer W TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 0% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 100% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 FTIOB Time Duty 100% Duty 0% Figure 11.
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Section 11 Timer W TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 100% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 0% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 0% FTIOB Duty 100% Figure 11.
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Section 11 Timer W 11.5 Operation Timing 11.5.1 TCNT Count Timing Figure 11.14 shows the TCNT count timing when the internal clock source is selected. Figure 11.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted correctly. φ Internal clock Rising edge TCNT input clock TCNT N N+1 N+2 Figure 11.
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Section 11 Timer W Figure 11.16 shows the output compare timing. φ TCNT input clock TCNT N GRA to GRD N N+1 Compare match signal FTIOA to FTIOD Figure 11.16 Output Compare Output Timing 11.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 11.17 shows the timing when the falling edge is selected.
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Section 11 Timer W 11.5.4 Timing of Counter Clearing by Compare Match Figure 11.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1. φ Compare match signal TCNT N GRA N H'0000 Figure 11.18 Timing of Counter Clearing by Compare Match 11.5.5 Buffer Operation Timing Figures 11.19 and 11.20 show the buffer operation timing. φ Compare match signal TCNT N GRC, GRD M GRA, GRB N+1 M Figure 11.
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Section 11 Timer W φ Input capture signal TCNT N GRA, GRB M GRC, GRD N+1 N N+1 M N Figure 11.20 Buffer Operation Timing (Input Capture) 11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register.
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Section 11 Timer W 11.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 11.22 shows the timing of the IMFA to IMFD flag setting at input capture. φ Input capture signal N TCNT N GRA to GRD IMFA to IMFD IRRTW Figure 11.22 Timing of IMFA to IMFD Flag Setting at Input Capture 11.5.
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Section 11 Timer W 11.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T2 state of a TCNT write cycle.
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Section 11 Timer W Previous clock New clock Count clock TCNT N N+1 N+2 N+3 The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 11.25 Internal Clock Switching and TCNT Operation Rev.4.00 Nov.
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Section 11 Timer W 5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and the generation of the compare match A to D occur at the same timing, the writing to TCRW has the priority.
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Section 12 Watchdog Timer Section 12 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 12.1.
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Section 12 Watchdog Timer 12.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value. Bit Bit Name Initial Value R/W 7 B6WI 1 R/W Description Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0.
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Section 12 Watchdog Timer Bit Bit Name Initial Value R/W Description 0 WRST 0 Watchdog Timer Reset R/W [Setting condition] When TCWD overflows and an internal reset signal is generated [Clearing conditions] 12.2.2 • Reset by RES pin • When 0 is written to the WRST bit while writing 0 to the B0WI bit when the TCSRWE bit = 1 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter.
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Section 12 Watchdog Timer 12.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 256 φosc clock cycles.
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Section 13 Serial Communication Interface 3 (SCI3) Section 13 Serial Communication Interface 3 (SCI3) Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
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Section 13 Serial Communication Interface 3 (SCI3) SCK3 External clock Internal clock (φ/64, φ/16, φ/4, φ) Baud rate generator BRC BRR SMR Transmit/receive control circuit SCR3 SSR TXD TSR TDR RXD RSR RDR [Legend] Receive shift register RSR: Receive data register RDR: Transmit shift register TSR: Transmit data register TDR: Serial mode register SMR: SCR3: Serial control register 3 Serial status register SSR: Bit rate register BRR: Bit rate counter BRC: Figure 13.1 Block Diagram of SCI3 Rev.
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Section 13 Serial Communication Interface 3 (SCI3) 13.2 Input/Output Pins Table 13.1 shows the SCI3 pin configuration. Table 13.1 Pin Configuration Pin Name Abbreviation I/O Function SCI3 clock SCK3 I/O SCI3 clock input/output SCI3 receive data input RXD Input SCI3 receive data input SCI3 transmit data output TXD Output SCI3 transmit data output 13.3 Register Descriptions The SCI3 has the following registers.
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Section 13 Serial Communication Interface 3 (SCI3) 13.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 13.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data.
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Section 13 Serial Communication Interface 3 (SCI3) 13.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator clock source. Bit Bit Name Initial Value R/W Description 7 COM 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length.
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Section 13 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the on-chip baud rate generator. 00: ø clock (n = 0) 01: ø/4 clock (n = 1) 10: ø/16 clock (n = 2) 11: ø/64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 13.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 13.
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Section 13 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
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Section 13 Serial Communication Interface 3 (SCI3) 13.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/W Transmit Data Register Empty Displays whether TDR contains transmit data.
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Section 13 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 4 FER 0 R/W Framing Error [Setting condition] • When a framing error occurs in reception [Clearing condition] • 3 PER 0 R/W When 0 is written to FER after reading FER = 1 Parity Error [Setting condition] • When a parity error is generated during reception [Clearing condition] • 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] • When the TE bit in S
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Section 13 Serial Communication Interface 3 (SCI3) 13.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 13.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 13.3 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 13.2 and 13.3 are values in active (highspeed) mode. Table 13.
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Section 13 Serial Communication Interface 3 (SCI3) Table 13.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 2 Bit Rate (bits/s) n 110 150 300 2.097152 2.4576 N n N Error (%) 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 –0.70 0 63 0.
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Section 13 Serial Communication Interface 3 (SCI3) Table 13.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728 8 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.
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Section 13 Serial Communication Interface 3 (SCI3) Table 13.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ (MHz) 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 181 0.16 2 191 0.00 2 207 0.16 300 2 90 0.16 2 95 0.00 2 103 0.16 600 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 181 0.16 0 191 0.
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Section 13 Serial Communication Interface 3 (SCI3) Table 13.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) n 2 N 4 n N 8 n N 10 n N 16 n N 110 3 70 — — — — — — 250 2 124 2 249 3 124 — — 3 249 500 1 249 2 124 2 249 — — 3 124 1k 1 124 1 249 2 124 — — 2 249 2.
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Section 13 Serial Communication Interface 3 (SCI3) 13.4 Operation in Asynchronous Mode Figure 13.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex.
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Section 13 Serial Communication Interface 3 (SCI3) 13.4.2 SCI3 Initialization Follow the flowchart as shown in figure 13.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
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Section 13 Serial Communication Interface 3 (SCI3) 13.4.3 Data Transmission Figure 13.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission.
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Section 13 Serial Communication Interface 3 (SCI3) Start transmission [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR Yes [2] All data transmitted? [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
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Section 13 Serial Communication Interface 3 (SCI3) 13.4.4 Serial Data Reception Figure 13.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit. 2.
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Section 13 Serial Communication Interface 3 (SCI3) Table 13.5 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.8 shows a sample flowchart for serial data reception. Table 13.
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Section 13 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR [2] No RDRF = 1 Yes Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically.
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Section 13 Serial Communication Interface 3 (SCI3) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 13.8 Sample Serial Reception Data Flowchart (2) Rev.4.00 Nov.
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Section 13 Serial Communication Interface 3 (SCI3) 13.5 Operation in Clocked Synchronous Mode Figure 13.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
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Section 13 Serial Communication Interface 3 (SCI3) 13.5.3 Serial Data Transmission Figure 13.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission.
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Section 13 Serial Communication Interface 3 (SCI3) Serial clock Serial data Bit 0 Bit 1 1 frame Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame TDRE TEND LSI TXI interrupt operation request generated TDRE flag cleared to 0 User processing Data written to TDR TXI interrupt request generated TEI interrupt request generated Figure 13.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode Rev.4.00 Nov.
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Section 13 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 Yes [2] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
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Section 13 Serial Communication Interface 3 (SCI3) 13.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 13.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. 2. 3. 4. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. The SCI3 stores the received data in RSR.
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Section 13 Serial Communication Interface 3 (SCI3) Start reception [1] [1] Read OER flag in SSR [2] Yes OER = 1 [4] No Error processing [3] (Continued below) Read RDRF flag in SSR [2] [4] No RDRF = 1 Yes Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0.
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Section 13 Serial Communication Interface 3 (SCI3) 13.5.5 Simultaneous Serial Data Transmission and Reception Figure 13.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
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Section 13 Serial Communication Interface 3 (SCI3) Start transmission/reception Read TDRE flag in SSR [1] [1] No TDRE = 1 Yes Write transmit data to TDR Read OER flag in SSR OER = 1 No Read RDRF flag in SSR Yes [4] Error processing [2] No RDRF = 1 Yes Read receive data in RDR Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
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Section 13 Serial Communication Interface 3 (SCI3) 13.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
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Section 13 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 13.
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Section 13 Serial Communication Interface 3 (SCI3) 13.6.1 Multiprocessor Serial Data Transmission Figure 13.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
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Section 13 Serial Communication Interface 3 (SCI3) 13.6.2 Multiprocessor Serial Data Reception Figure 13.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure 13.
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Section 13 Serial Communication Interface 3 (SCI3) [1] [2] Start reception Set MPIE bit in SCR3 to 1 [1] Read OER and FER flags in SSR [2] [3] Yes FER+OER = 1 No Read RDRF flag in SSR [3] No [4] [5] RDRF = 1 Yes Read receive data in RDR No This station’s ID? Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs.
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Section 13 Serial Communication Interface 3 (SCI3) [5] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No [A] Framing error processing Clear OER, and FER flags in SSR to 0 Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev.4.00 Nov.
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Section 13 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation User processing RXI interrupt request is not generated, and RDR retains its state RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again (a)
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Section 13 Serial Communication Interface 3 (SCI3) 13.7 Interrupts The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 13.6 shows the interrupt sources. Table 13.
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Section 13 Serial Communication Interface 3 (SCI3) 13.8 Usage Notes 13.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 13.8.
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Section 13 Serial Communication Interface 3 (SCI3) 13.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 13.19.
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Section 14 A/D Converter Section 14 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to four analog input channels to be selected. The block diagram of the A/D converter is shown in figure 14.1. 14.1 • • • • • • • • Features 10-bit resolution Four input channels Conversion time: at least 4.
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Section 14 A/D Converter Module data bus AN0 AN1 AN2 AN3 Analog multiplexer 10-bit D/A Bus interface Successive approximations register AVCC Internal data bus A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + φ/4 Control circuit Comparator Sample-andhold circuit ADTRG [Legend] ADCR : ADCSR : ADDRA : ADDRB : ADDRC : ADDRD : A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 14.
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Section 14 A/D Converter 14.2 Input/Output Pins Table 14.1 summarizes the input pins used by the A/D converter. Table 14.1 Pin Configuration Pin Name Symbol I/O Function Analog power supply pin AVCC Input Analog block power supply pin Analog input pin 0 AN0 Input Analog input pins Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 A/D external trigger input pin ADTRG Input Input External trigger input pin for starting A/D conversion Rev.4.00 Nov.
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Section 14 A/D Converter 14.3 Register Description The A/D converter has the following registers. • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 14.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion.
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Section 14 A/D Converter 14.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter.
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Section 14 A/D Converter Bit Bit Name Initial Value R/W Description 2 CH2 0 R/W Channel Select 0 to 2 1 CH1 0 R/W Select analog input channels. 0 CH0 0 R/W When SCAN = 0 Legend: 14.3.3 When SCAN = 1 X00: AN0 X00: AN0 X01: AN1 X01: AN0 to AN1 X10: AN2 X10: AN0 to AN2 X11: AN3 X11: AN0 to AN3 X: Don't care. A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal.
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Section 14 A/D Converter 14.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 14.4.
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Section 14 A/D Converter 14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 14.2 shows the A/D conversion timing. Table 14.3 shows the A/D conversion time. As indicated in figure 14.2, the A/D conversion time includes tD and the input sampling time.
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Section 14 A/D Converter Table 14.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max A/D conversion start delay tD 6 — 9 4 — 5 Input sampling time tSPL — 31 — — 15 — A/D conversion time tCONV 131 — 134 69 — 70 Note: All values represent the number of states. 14.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
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Section 14 A/D Converter 14.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14.4). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 14.5).
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Section 14 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 14.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 14.5 A/D Conversion Accuracy Definitions (2) Rev.4.00 Nov.
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Section 14 A/D Converter 14.6 Usage Notes 14.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
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Section 15 Power Supply Circuit Section 15 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V.
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Section 15 Power Supply Circuit 15.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 15.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
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Section 16 List of Registers Section 16 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. • • • • Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated. 2.
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Section 16 List of Registers 16.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
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Section 16 List of Registers Register Name Abbreviation Module Bit No Address Name Data Bus Width Access State Transmit data register TDR 8 H'FFAB SCI3 8 3 Serial status register SSR 8 H'FFAC SCI3 8 3 Receive data register RDR 8 H'FFAD SCI3 8 3 A/D data register A ADDRA 16 H'FFB0 A/D converter 8 3 A/D data register B ADDRB 16 H'FFB2 A/D converter 8 3 A/D data register C ADDRC 16 H'FFB4 A/D converter 8 3 A/D data register D ADDRD 16 H'FFB6 A/D converter 8
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Section 16 List of Registers Bit No Address Module Name Data Bus Access Width State PDRB 8 H'FFDD I/O port 8 2 Port mode register 1 PMR1 8 H'FFE0 I/O port 8 2 Port mode register 5 PMR5 8 H'FFE1 I/O port 8 2 Port control register 1 PCR1 8 H'FFE4 I/O port 8 2 Port control register 2 PCR2 8 H'FFE5 I/O port 8 2 Port control register 5 PCR5 8 H'FFE8 I/O port 8 2 Port control register 7 PCR7 8 H'FFEA I/O port 8 2 Port control register 8 PCR8 8 H'FFEB I/O por
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Section 16 List of Registers 16.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines.
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Section 16 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name SCR3 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI3 TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SSR TDRE RDRF OER FER PER TEND MPBR MPBT RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 ADDRA AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 A
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Section 16 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name PDRB — — — — PB3 PB2 PB1 PB0 I/O port PMR1 IRQ3 — — IRQ0 — — TXD — PMR5 POF7 POF6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 PCR1 PCR17 PCR16 PCR15 PCR14 — PCR12 PCR11 PCR10 PCR2 — — — — — PCR22 PCR21 PCR20 PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 PCR7 — PCR76 PCR75 PCR74 — — — — PCR8 — — — PCR84 PCR83 PCR82 PCR81 PCR80 SYSCR
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Section 16 List of Registers 16.
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Section 16 List of Registers Register Name Reset Active Sleep Subsleep Standby Module ADDRA Initialized — — Initialized Initialized A/D converter ADDRB Initialized — — Initialized Initialized ADDRC Initialized — — Initialized Initialized ADDRD Initialized — — Initialized Initialized ADCSR Initialized — — Initialized Initialized ADCR Initialized — — Initialized Initialized TCSRWD Initialized — — — — TCWD Initialized — — — — TMWD Initialized — — — —
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Section 16 List of Registers Register Name Reset Active Sleep Subsleep Standby Module SYSCR1 Initialized — — — — Power-down SYSCR2 Initialized — — — — IEGR1 Initialized — — — — IEGR2 Initialized — — — — IENR1 Initialized — — — — IRR1 Initialized — — — — IWPR Initialized — — — — MSTCR1 Initialized — — — — Notes:  is not initialized * WDT: Watchdog timer Rev.4.00 Nov.
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Section 17 Electrical Characteristics Section 17 Electrical Characteristics 17.1 Absolute Maximum Ratings Table 17.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +7.0 V * Analog power supply voltage AVCC –0.3 to +7.0 V Input voltage VIN Ports other than Port B Port B –0.3 to VCC +0.3 V –0.3 to AVCC +0.
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Section 17 Electrical Characteristics Power Supply Voltage and Operating Frequency Range φ (MHz) 16.0 10.0 1.0 3.0 4.0 5.5 VCC (V) • AVCC = 3.3 V to 5.5 V • Active mode • Sleep mode (When MA2 = 0 in SYSCR2) φ (kHz) 2000 1250 78.125 3.0 4.0 5.5 VCC (V) • AVCC = 3.3 V to 5.5 V • Active mode • Sleep mode (When MA2 = 1 in SYSCR2) Rev.4.00 Nov.
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Section 17 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range φ (MHz) 16.0 10.0 2.0 3.3 4.0 5.5 AVCC (V) • VCC = 3.0 V to 5.5 V • Active mode • Sleep mode Rev.4.00 Nov.
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Section 17 Electrical Characteristics 17.2.2 DC Characteristics Table 17.2 DC Characteristics (1) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Input high VIH voltage VCC = 4.0 V to 5.5 V RES, NMI, WKP0 to WKP5, IRQ0, IRQ3, ADTRG,TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV RXD, P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P74, P84 to P80 VCC = 4.0 V to 5.5 V PB3 to PB0 VCC = 4.0 V to 5.
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Section 17 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Output high voltage VOH P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P74, P84 to P80 VCC = 4.0 V to 5.5 V VCC – 1.0 — Output low voltage VOL P12 to P10, P17 to P14, P22 to P20, P55 to P50, P76 to P74 P84 to P80 Min Typ Max Unit — V Notes –IOH = 1.5 mA –IOH = 0.1 mA VCC – 0.5 — VCC = 4.0 V to 5.5 V — — — 0.6 — — 0.4 VCC = 4.0 V to 5.5 V — — 1.5 — 1.0 — 0.4 — 0.4 V IOL = 1.
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Section 17 Electrical Characteristics Values Item Symbol Applicable Pins Input/ output leakage current | IIL | Min Typ Max Unit OSC1, RES, ,NMI, VIN = 0.5 V to WKP0 to WKP5, (VCC – 0.5 V) IRQ0, IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, RXD, SCK3 — — 1.0 µA P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P74, P84 to P80 VIN = 0.5 V to (VCC – 0.5 V) — — 1.0 µA PB3 to PB0 VIN = 0.5 V to (AVCC – 0.5 V) — — 1.0 µA P12 to P10, P17 to P14, P55 to P50 VCC = 5.
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Section 17 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes Sleep mode current consumption ISLEEP1 VCC Sleep mode 1 VCC = 5.0 V, fOSC = 16 MHz — 11.5 17.0 mA * Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz — 6.5 — Sleep mode 2 VCC = 5.0 V, fOSC = 16 MHz — 1.7 2.5 Sleep mode 2 VCC = 3.0 V, fOSC = 10 MHz — 1.1 — 32-kHz crystal resonator not used — — 5.0 µA 2.
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Section 17 Electrical Characteristics Mode RES Pin Internal State Other Pins Oscillator Pins Active mode 1 VCC Operates VCC Main clock: ceramic or crystal resonator Active mode 2 Operates (φOSC/64) Sleep mode 1 VCC Only timers operate Sleep mode 2 VCC Only timers operate (φOSC/64) Standby mode VCC CPU and timers both stop VCC Main clock: ceramic or crystal resonator Table 17.2 DC Characteristics (2) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated.
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Section 17 Electrical Characteristics 17.2.3 AC Characteristics Table 17.3 AC Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Item Symbol System clock oscillation frequency fOSC System clock (ø) cycle time tcyc Applicable Pins OSC1, OSC2 Instruction cycle time Values Typ Max Unit Reference Figure VCC = 4.0 V to 5.5 V 2.0 — 16.0 MHz * 2.0 — 10.0 MHz 1 — 64 tOSC — — 12.
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Section 17 Electrical Characteristics Item Symbol Applicable Pins RES pin low width tREL RES Values Typ Max Unit Reference Figure At power-on and in trc modes other than those below — — ms Figure 17.
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Section 17 Electrical Characteristics Table 17.4 Serial Interface (SCI3) Timing VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Item Input clock cycle Asynchronous Symbol Applicable Pins tScyc SCK3 Values Test Condition Clocked synchronous Input clock pulse width tSCKW SCK3 Transmit data delay time (clocked synchronous) tTXD TXD Receive data setup time (clocked synchronous) tRXS Receive data hold time (clocked synchronous) tRXH RXD RXD VCC = 4.
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Section 17 Electrical Characteristics 17.2.4 A/D Converter Characteristics Table 17.5 A/D Converter Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Item Symbol Applicable Pins Test Condition Values Min Typ Max Unit Reference Figure V * Analog power supply AVCC voltage AVCC 3.3 VCC 5.5 Analog input voltage AN3 to AN0 VSS – 0.3 — AVCC + 0.3 V — 2.0 mA AVIN Analog power supply AIOPE current AVCC AVCC = 5.
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Section 17 Electrical Characteristics Item Symbol Applicable Pins Conversion time (single mode) Test Condition Values Min AVCC = 4.0 V 134 to 5.5 V Typ Max Unit — — tcyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Reference Figure Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2.
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Section 17 Electrical Characteristics 17.2.6 Flash Memory Characteristics Table 17.7 Flash Memory Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
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Section 17 Electrical Characteristics Item Erase Symbol Test Condition Values Min Typ Max Unit Wait time after SWE 1 bit setting* x 1 — — µs Wait time after ESU 1 bit setting* y 100 — — µs Wait time after E bit 1 6 setting* * z 10 — 100 ms Wait time after E bit clear* α 10 — — µs Wait time after ESU 1 bit clear* β 10 — — µs Wait time after EV 1 bit setting* γ 20 — — µs Wait time after 1 dummy write* ε 2 — — µs Wait time after EV bit clear* η 4 — — µs W
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Section 17 Electrical Characteristics 17.3 Operation Timing t OSC VIH OSC1 VIL t CPH t CPL t CPf t CPr Figure 17.1 System Clock Input Timing VCC VCC × 0.7 OSC1 tREL RES VIL VIL tREL Figure 17.2 RES Low Width Timing NMI, IRQ0, IRQ3 WKP0 to WKP5 ADTRG FTCI FTIOA to FTIOD TMCIV, TMRIV TRGV VIH VIL t IL t IH Figure 17.3 Input Timing Rev.4.00 Nov.
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Section 17 Electrical Characteristics t SCKW SCK3 t Scyc Figure 17.4 SCK3 Input Clock Timing t Scyc SCK3 VIH or VOH * VIL or VOL * t TXD * TXD (transmit data) VOH VOL * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high: V OH= 2.0 V Output low: V OL= 0.8 V Load conditions are shown in figure 17.6. Figure 17.5 SCI3 Input/Output Timing in Clocked Synchronous Mode Rev.4.00 Nov.
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Section 17 Electrical Characteristics 17.4 Output Load Condition VCC 2.4 kΩ LSI output pin 30 pF 12 k Ω Figure 17.6 Output Load Circuit Rev.4.00 Nov.
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Appendix Appendix A Instruction Set A.
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Appendix Symbol Description ↔ Condition Code Notation Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev.4.00 Nov.
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Appendix Table A.1 Instruction Set 1. Data transfer instructions Condition Code MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) → Rd8 — — MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) → Rd8 — — MOV.B @ERs+, Rd B @ERs → Rd8 ERs32+1 → ERs32 — — MOV.B @aa:8, Rd B 2 @aa:8 → Rd8 — — MOV.B @aa:16, Rd B 4 @aa:16 → Rd8 — — MOV.B @aa:24, Rd B 6 @aa:24 → Rd8 — — MOV.B Rs, @ERd B Rs8 → @ERd — — MOV.B Rs, @(d:16, ERd) B 4 Rs8 → @(d:16, ERd) — — MOV.
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Appendix No. of States*1 Condition Code — — @(d:24, ERs) → ERd32 — — @ERs → ERd32 ERs32+4 → ERs32 — — 6 @aa:16 → ERd32 — — 8 @aa:24 → ERd32 — — ERs32 → @ERd — — ERs32 → @(d:16, ERd) — — ERs32 → @(d:24, ERd) — — ERd32–4 → ERd32 ERs32 → @ERd — — 6 ERs32 → @aa:16 — — 8 ERs32 → @aa:24 — — 0 — 0 — POP POP.W Rn W 2 @SP → Rn16 SP+2 → SP — — POP.L ERn L 4 @SP → ERn32 SP+4 → SP — — 0 — PUSH PUSH.W Rn W 2 SP–2 → SP Rn16 → @SP — — 0 — PUSH.
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Appendix 2. Arithmetic instructions No. of States*1 Condition Code Z V C ↔ ↔ — (2) ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ERd32+ERs32 → ERd32 — (2) ↔ ↔ (3) ↔ ↔ Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ERd32 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ADDS ADDS.L #1, ERd L 2 ERd32+1 → ERd32 — — — — — — 2 ADDS.L #2, ERd L 2 ERd32+2 → ERd32 — — — — — — 2 ADDS.L #4, ERd L 2 ERd32+4 → ERd32 — — — — — — 2 INC.B Rd B 2 Rd8+1 → Rd8 — — INC.W #1, Rd W 2 Rd16+1 → Rd16 — — INC.
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Appendix No. of States*1 Condition Code Advanced V C ERd32–1 → ERd32 — — L 2 ERd32–2 → ERd32 — — ↔ ↔ — 2 DAS.Rd B 2 Rd8 decimal adjust → Rd8 — * ↔ ↔ ↔ 2 DEC.L #2, ERd ↔ ↔ ↔ — * — 2 B 2 Rd8 × Rs8 → Rd16 (unsigned multiplication) — — — — — — 14 W 2 Rd16 × Rs16 → ERd32 (unsigned multiplication) — — — — — — 22 B 4 Rd8 × Rs8 → Rd16 (signed multiplication) — — ↔ W 4 Rd16 × Rs16 → ERd32 (signed multiplication) — — B 2 W DIVXU DIVXU. B Rs, Rd DIVXU.
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Appendix No. of States*1 L 0–ERd32 → ERd32 2 — EXTU EXTU.W Rd W 0 → ( of Rd16) 2 — — 0 L 0 → ( of ERd32) 2 — — 0 W ( of Rd16) → ( of Rd16) 2 — — L ( of ERd32) → ( of ERd32) 2 — — Advanced NEG.L ERd Normal ↔ ↔ ↔ — ↔ ↔ ↔ ↔ ↔ ↔ 2 ↔ ↔ ↔ C ↔ ↔ ↔ ↔ W 0–Rd16 → Rd16 EXTS.L ERd V 2 0 — 2 ↔ NEG.W Rd EXTS EXTS.W Rd Z 0 — 2 ↔ — 0 — 2 ↔ H 2 EXTU.L ERd N ↔ I B 0–Rd8 → Rd8 NEG NEG.
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Appendix 3. Logic instructions AND.B Rs, Rd B AND.W #xx:16, Rd W 4 AND.W Rs, Rd W AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W 4 OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W 4 XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L 4 ERd32⊕ERs32 → ERd32 — — NOT.B Rd B 2 ¬ Rd8 → Rd8 — — NOT.W Rd W 2 ¬ Rd16 → Rd16 — — NOT.
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Appendix 4. Shift instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 ROTXR ROTXR.
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Appendix 5.
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Appendix B BLD #xx:3, @aa:8 B BILD BILD #xx:3, Rd B BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BIST BST #xx:3, @aa:8 B BST BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd B BAND #xx:3, @ERd B BIAND BAND #xx:3, @aa:8 B BOR BIAND #xx:3, Rd B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #
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Appendix 6.
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Appendix JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — No.
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Appendix 7. System control instructions No.
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Appendix 8. Block transfer instructions EEPMOV No. of States*1 H N Z V C Normal — @@aa @(d, PC) I EEPMOV. B — 4 if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next — — — — — — 8+ 4n*2 EEPMOV.
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REJ09B0143-0400 Rev.4.00 Nov. 02, 2005 Page 260 of 304 MULXU 5 STC LDC 3 SUBX OR XOR AND MOV C D E F BILD BIST BLD BST TRAPA BEQ B BIAND BAND AND RTE BNE CMP BIXOR BXOR XOR BSR BCS A BIOR BOR OR RTS BCC MOV.B Table A-2 (2) LDC 7 ADDX BTST DIVXU BLS AND.B ANDC 6 9 BCLR MULXU BHI XOR.B XORC 5 ADD BNOT DIVXU BRN OR.
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MOV 7A BRA 58 MOV DAS 1F 79 SUBS 1B 1 CMP CMP ADD BHI 2 ADD BRN NOT 17 DEC ROTXR 13 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 SUB SUB BLS OR OR XOR XOR BCS AND AND BEQ BVC SUB 9 BVS NEG NOT DEC ROTR ROTXR DEC ROTL ADDS SLEEP 8 ROTXL EXTU INC 7 SHAR BNE 6 SHLR EXTU INC 5 SHAL BCC LDC/STC 4 SHLL 3 1st byte 2nd byte AH AL BH BL BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Table
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REJ09B0143-0400 Rev.4.00 Nov. 02, 2005 Page 262 of 304 DIVXS 3 BSET 7Faa7 * 2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field.
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Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
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Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM — Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. See section 16.1, Register Addresses (Address Order). Rev.4.00 Nov.
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Appendix Table A.4 Number of Cycles in Each Instruction Instruction Branch Addr. Stack Instruction Mnemonic FetchI Read J ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.
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Appendix Instruction Mnemonic Bcc BCLR BIAND BILD Instruction Branch Fetch I Addr.
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Appendix Instruction Branch Instruction Mnemonic Fetch I Addr.
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Appendix Instruction Branch Addr. Stack Byte Data Word Data Internal Instruction Mnemonic Fetch I Read J Access L Access M Operation N BTST BTST #xx:3, Rd 1 BTST #xx:3, @ERd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @ERd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 BXOR #xx:3, @ERd 2 1 BXOR #xx:3, @aa:8 2 1 CMP.B #xx:8, Rd 1 CMP.B Rs, Rd 1 CMP.W #xx:16, Rd 2 CMP.W Rs, Rd 1 CMP.L #xx:32, ERd 3 CMP.L ERs, ERd 1 DAA DAA Rd 1 DAS DAS Rd 1 DEC DEC.
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Appendix Instruction Branch Addr. Stack Instruction Mnemonic Fetch I Read J INC INC.B Rd 1 INC.W #1/2, Rd 1 JMP JSR LDC MOV INC.
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Appendix Instruction Branch Addr. Stack Instruction Mnemonic Fetch I Read J MOV MOV.B Rs, @aa:16 2 1 MOV.B Rs, @aa:24 3 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 1 MOV.W @(d:16,ERs), Rd 2 1 MOV.W @(d:24,ERs), Rd 4 1 MOV.W @ERs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W @aa:24, Rd 3 1 MOV.W Rs, @ERd MOV Byte Data Operation K Access L Word Data Internal Access M Operation N 1 1 MOV.W Rs, @(d:16,ERd) 2 1 MOV.W Rs, @(d:24,ERd) 4 1 MOV.W Rs, @-ERd 1 1 MOV.
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Appendix Instruction Branch Addr. Stack Instruction Mnemonic Fetch I Read J MULXS MULXS.B Rs, Rd 2 12 MULXS.W Rs, ERd 2 20 MULXU.B Rs, Rd 1 12 MULXU.W Rs, ERd 1 20 NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 NOP 1 MULXU NEG NOP NOT OR NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 OR.
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Appendix Instruction Branch Addr. Stack Instruction Mnemonic Fetch I Read J ROTXR ROTXR.B Rd 1 ROTXR.W Rd 1 Byte Data Operation K Access L Word Data Internal Access M Operation N ROTXR.L ERd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL.B Rd 1 SHAL.W Rd 1 SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 SHLR.
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Appendix Instruction Branch Addr. Stack Instruction Mnemonic Fetch I Read J Operation K Access L SUBX SUBX #xx:8, Rd 1 SUBX. Rs, Rd 1 TRAPA #xx:2 2 1 2 TRAPA XOR XORC XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 Byte Data Word Data Internal Access M Operation N 4 Notes: 1. n:specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2.
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Appendix A.4 Combinations of Instructions and Addressing Modes Table A.
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Appendix Appendix B I/O Port Block Diagrams B.1 I/O Port Block RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev.4.00 Nov.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P14) Rev.4.00 Nov.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PDR PCR [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.3 Port 1 Block Diagram (P16, P15, P12, P10) Rev.4.00 Nov.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PDR PCR [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.4 Port 1 Block Diagram (P11) Rev.4.00 Nov.
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Appendix Internal data bus SBY PMR PDR PCR SCI3 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.5 Port 2 Block Diagram (P22) Rev.4.00 Nov.
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Appendix SBY Internal data bus PDR PCR SCI3 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.6 Port 2 Block Diagram (P21) Rev.4.00 Nov.
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Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.7 Port 2 Block Diagram (P20) Rev.4.00 Nov.
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Appendix Internal data bus SBY PMR PDR PCR [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.8 Port 5 Block Diagram (P57, P56) Rev.4.00 Nov.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.9 Port 5 Block Diagram (P55) Rev.4.00 Nov.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.10 Port 5 Block Diagram (P54 to P50) Rev.4.00 Nov.
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Appendix Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.11 Port 7 Block Diagram (P76) Rev.4.00 Nov.
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Appendix Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.12 Port 7 Block Diagram (P75) Rev.4.00 Nov.
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Appendix Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.13 Port 7 Block Diagram (P74) Rev.4.00 Nov.
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Appendix Internal data bus SBY Timer W Output control signals A to D PDR PCR FTIOA FTIOB FTIOC FTIOD [Legend] PDR: Port data register PCR: Port control register Figure B.14 Port 8 Block Diagram (P84 to P81) Rev.4.00 Nov.
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Appendix Internal data bus SBY PDR PCR Timer W FTCI [Legend] PDR: Port data register PCR: Port control register Figure B.15 Port 8 Block Diagram (P80) Rev.4.00 Nov.
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Appendix Internal data bus A/D converter DEC CH3 to CH0 VIN Figure B.16 Port B Block Diagram (PB3 to PB0) Rev.4.00 Nov.
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Appendix B.
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Appendix Appendix C Product Code Lineup Product Type H8/3672 H8/3670 Model Marking Package Code Flash memory Standard HD64F3672FP version product HD64F3672FP LQFP-64 (FP-64E) HD64F3672FX HD64F3672FX LQFP-48 (FP-48F) HD64F3672FY HD64F3672FY LQFP-48 (FP-48B) Flash memory Standard HD64F3672FP version product HD64F3672FP LQFP-64 (FP-64E) HD64F3670FX HD64F3670FX LQFP-48 (FP-48F) HD64F3670FY HD64F3670FY LQFP-48 (FP-48B) Rev.4.00 Nov.
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64 49 e ZD 1 48 *1 y *3 bp Index mark D 16 33 x F M 17 32 MASS[Typ.] 0.4g Detail F L1 L Terminal cross section b1 bp θ NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 HD E *2 Previous Code FP-64E/FP-64EV A2 A1 c RENESAS Code PLQP0064KC-A c A HE JEITA Package Code P-LQFP64-10x10-0.50 11.8 0.20 0.5 L 1.0 1.25 ZE L1 1.25 ZD 0.7 0.08 8° 0.22 0.10 0.5 0.15 0.17 0.27 y 0.3 0° 0.12 0.
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Figure D.2 FP-48F Package Dimensions 48 e ZD 1 *3 bp y Index mark D HD 12 25 x M F 13 24 E *2 37 36 *1 Previous Code FP-48F/FP-48FV MASS[Typ.] 0.4g Detail F L1 L Terminal cross section b1 bp θ 11.8 HD HE 0.1 0.5 L 1.0 1.425 ZE L1 1.425 ZD 0.6 0.10 8° 0.22 0.13 0.65 0.15 0.17 0.37 y 0.4 0° 0.12 0.30 x e θ c1 c b1 0.32 0.15 0.27 A1 bp 1.70 12.2 12.2 Max A 0.05 12.0 11.8 A2 12.0 10 1.
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48 e ZD 1 D HD *3 bp y 12 25 x M F 13 24 E *2 37 36 *1 MASS[Typ.] 0.2g Detail F L1 L Terminal cross section b1 bp θ 7 0.10 0.17 L1 1.0 0.5 0.75 ZE L 0.75 ZD 0.6 0.08 8° 0.22 0.27 0.08 0.5 0.15 0.17 0.20 0.22 y 0.4 0° 0.12 0.17 1.70 9.2 9.2 Max x e θ c1 c b1 bp A1 0.03 9.0 8.8 HE A 9.0 8.8 HD 1.40 E A2 7 Nom Dimension in Millimeters Min D Reference Symbol NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2.
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Appendix Rev.4.00 Nov.
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Main Revisions and Additions in this Edition Item Page Revisions (See Manual for Details) Preface vi, vii When using the on-chip emulator (E7, E8) for H8/3672 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Area H'4000 to H'4FFF is used by the E7 or E8, and is not available to the user. 4. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8.
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Item Page Section 2 CPU Figure 2.
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Item Page Revisions (See Manual for Details) Section 8 RAM 93 Note has been added. Section 10 Timer V 120 10.3.4 Timer Control/Status Register V (TCSRV) Bit Bit Name Description 3 OS3 Output Select 3 and 2 2 OS2 These bits select an output method for the TMOV pin by the compare match of TCORB and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles Section 12 Watchdog Timer 12.2.
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Item Page Table 17.2 DC Characteristics (1) 234 Revisions (See Manual for Details) Mode RES Pin Internal State Active mode 1 VCC Operates Active mode 2 Sleep mode 1 Operates (φOSC/64) VCC Sleep mode 2 Appendix D Package Dimensions 293 to Swapped with new ones. 295 Rev.4.00 Nov.
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Index A A/D Converter ........................................ 203 A/D conversion time........................... 210 external trigger input........................... 211 sample-and-hold circuit ...................... 210 Scan Mode .......................................... 209 Single Mode........................................ 209 Absolute Maximum Ratings ................... 227 Address Break........................................... 55 Addressing Modes ....................................
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Internal Power Supply Step-Down Circuit.................................. 215 Interrupt Internal Interrupts ................................. 49 Interrupt Response Time ...................... 51 IRQ3 to IRQ0 Interrupts....................... 48 NMI interrupt........................................ 48 WKP5 to WKP0 Interrupts................... 49 L large current ports....................................... 1 M Memory Map .............................................. 8 Module Standby Function .............
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PMR1............................ 96, 220, 223, 225 PMR5.......................... 103, 220, 223, 225 PUCR1.......................... 98, 219, 222, 225 PUCR5........................ 105, 219, 222, 225 RDR............................ 166, 219, 222, 224 RSR..................................................... 166 SCR3........................... 168, 218, 222, 224 SMR............................ 167, 218, 221, 224 SSR ............................. 170, 219, 222, 224 SYSCR1 .......................
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Rev.4.00 Nov.
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Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/3672 Group Publication Date: 1st Edition, Mar, 2001 Rev.4.00, Nov. 02, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2005. Renesas Technology Corp. All rights reserved. Printed in Japan.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.
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H8/3672 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0143-0400