Datasheet

Rev. 6.00 Mar. 24, 2006 Page 406 of 412
REJ09B0142-0600
Item Page Revision (See Manual for Details)
15.5 Usage Notes
• Notes on WAIT Function
• Notes on TRS Bit Setting and
ICDR Register Access
271 to
274
Added.
16.3.1 A/D Data Registers A to D
(ADDRA to ADDRD)
278 Amended
… Therefore, byte access to ADDR should be done by
reading the upper byte first then the lower one. Word
access is also possible. ADDR is initialized to H'0000.
Table 20.2 DC Characteristics (1) 314 Amended
Values
Item Applicable Pins Test Condition Min
Input high
voltage
PB0 to PB7 V
CC
= 4.0 V to 5.5 V V
CC
× 0.7
AV
CC
= 3.3 V to 5.5 V V
CC
× 0.8
Input low
voltage
P50 to P57*,
P74 to P76,
P80 to P87,
PB0 to PB7
–0.3
Pb0 to PB7 AV
CC
= 4.0 V to 5.5 V –0.3
AV
CC
= 3.3 V to 5.5 V –0.3
Table 20.2 DC Characteristics (1)
Table 20.10 DC Characteristics
(1)
318,
335
Amended
Note: * Pin states during supply current
measurement are given below (excluding
current in the pull-up MOS transistors and
output buffers).
Mode RES Pin Internal State
Active mode 1 V
CC
Operates
Active mode 2 Operates
(φosc/64)
Sleep mode 1 V
CC
Only timers operate
Sleep mode 2 Only timers operate
(φosc/64)