Datasheet

Rev. 6.00 Mar. 24, 2006 Page 404 of 412
REJ09B0142-0600
Item Page Revision (See Manual for Details)
6.1.1 System Control Register 1
(SYSCR1)
85 Amended
Bit Bit Name Description
3 NESEL Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch
clock signal (φ
W
) and the system clock pulse
generator generates the oscillator clock (φ
OSC
). This
bit selects the sampling frequency of the oscillator
clock when the watch clock signal (φ
W
) is sampled.
When φ
OSC
= 4 to 16 MHz, clear NESEL to 0.
0: Sampling rate is φ
OSC
/16
1: Sampling rate is φ
OSC
/4
Table 7.2 Boot Mode Operation 102 Amended
Communication Contents
Processing Contents
Host Operation
LSI Operation
Processing Contents
Continuously transmits data H'00
at specified bit rate.
H'00, H'00
. . .
H'00
H'00
H'55
H'55 reception.
Transmits data H'55 when data H'00
is received error-free.
Item
• Measures low-level period of receive data
H'00.
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
end indication.
Bit rate adjustment
9.5.3 Pin Functions
• P84/FTIOD Pin
136 Amended
Register TMRW TIOR1 PCR8
Bit Name
PWMD IOD2 IOD1 IOD0 PCR84 Pin Function
0 0 0 0 0 P84 input/FTIOD input pin
1 P84 output/FTIOD input pin
0 0 1 X FTIOD output pin
0 1 X X FTIOD output pin
1 X X 0 P84 input/FTIOD input pin
1 P84 output/FTIOD input pin
Setting Value
1 X X X X PWM output pin