Datasheet

Section 20 Electrical Characteristics
Rev. 6.00 Mar. 24, 2006 Page 339 of 412
REJ09B0142-0600
Table 20.12 I
2
C Bus Interface Timing
Values Test Reference
Item Symbol Min Typ Max Unit Condition Figure
SCL input cycle time t
SCL
12t
cyc
+ 600 — — ns Figure 20.4
SCL input high width t
SCLH
3t
cyc
+ 300 — — ns
SCL input low width t
SCLL
5t
cyc
+ 300 — — ns
Input fall time of
SCL and SDA
t
Sf
— — 300 ns
SCL and SDA input
spike pulse removal
time
t
SP
— — 1t
cyc
ns
SDA input bus-free
time
t
BUF
5t
cyc
— — ns
Start condition input
hold time
t
STAH
3t
cyc
— — ns
Retransmission start
condition input setup
time
t
STAS
3t
cyc
— — ns
Setup time for stop
condition input
t
STOS
3t
cyc
— — ns
Data-input setup time t
SDAS
1t
cyc
+20 — — ns
Data-input hold time t
SDAH
0 — — ns
Capacitive load of
SCL and SDA
c
b
0 — 400 pF
SCL and SDA output
fall time
t
Sf
— — 250 ns V
CC
= 4.0 V
to 5.5 V
— — 300 ns