Datasheet

Section 17 EEPROM
Rev. 6.00 Mar. 24, 2006 Page 287 of 412
REJ09B0142-0600
Section 17 EEPROM
This LSI has an on-chip 512-byte EEPROM. The block diagram of the EEPROM is shown in
figure 17.1.
17.1 Features
• Two writing methods:
1-byte write
Page write: Page size 8 bytes
• Three reading methods:
Current address read
Random address read
Sequential read
• Acknowledge polling possible
• Write cycle time:
10 ms (power supply voltage Vcc = 2.7 V or more)
• Write/Erase Endurance:
10
4
cycles/byte (byte write mode), 10
5
cycles/page (page write mode)
• Data retention:
10 years after the write cycle of 10
4
cycles (page write mode)
• Interface with the CPU
I
2
C bus interface (complies with the standard of Philips Corporation)
Device code 1010
Sleep address code can be changed (initial value: 000))
The I
2
C bus is open to the outside, so the EEPROM can be directly accessed from the outside.