Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 273 of 412
REJ09B0142-0600
SDA
SCL
TRS bit
TDRE bit
(b) TRS = 1
(a) TDRE = 0
TRS = 0 setting ICDR write
Automatic TRS = 1 setting by
receiving R/W = 1
Start conditionStop condition
DataAAddressA
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Cancel condition of SCL =
Low fixation is set.
Along with ICDRT → ICDRR transfer
Figure 15.20 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode
 Restriction
Please carry out the following countermeasures when transmitting/receiving via the IIC bus
interface module.
(1) Please read the ICDR registers in receive mode, and write them in transmit mode.
(2) In receiving operation with master mode, please issue the start condition after clearing
the internal flag of the IIC bus interface module, using CLR3 to CLR0 bit of the
DDCSWR register on bus-free state (BBSY = 0).