Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 272 of 412
REJ09B0142-0600
• Notes on TRS Bit Setting and ICDR Register Access
 Conditions to cause this failure
Low-fixation of the SCL pins is cancelled incorrectly when the following conditions are
satisfied.
Master mode:
Figure 15.19 shows the notes on ICDR reading (TRS = 1) in master mode.
(a) When previously received 2-byte data remains in ICDR unread (ICDRS are full).
(b) Reads ICDR register after switching to transmit mode (TRS = 1). (RDRF = 0 state)
(c) Sets to receive mode (TRS = 0), after transmitting the first frame of issued start
condition by master mode.
Slave mode:
Figure 15.20 shows the notes on ICDR writing (TRS = 0) in slave mode.
(a) Writes ICDR register in receive mode (TRS = 0), after entering the start condition by
slave mode (TDRE = 0 state).
(b) Address match with the first frame, receive 1 by R/W bit, and switches to transmit
mode (TRS = 1).
When these conditions are satisfied, the low fixation of the SCL pins is cancelled without
ICDR register access after the first frame is transferred.
SDA
SCL
TRS bit
RDRF bit
ICDRS data full
(c) TRS = 0
(b) RDRF = 0
(a) ICDRS data full
ICDR read
TRS = 0 setting
Stop condition Start condition
DataAAddressA
89 123456789 123
Cancel condition of SCL =
Low fixation is set.
Along with ICDRS → ICDRR transfer
Detection of 9th clock rise
(TRS = 1)
Figure 15.19 Notes on ICDR Reading with TRS = 1 Setting in Master Mode