Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 267 of 412
REJ09B0142-0600
5. The I
2
C bus interface specification for the SCL rise time t
sr
is under 1000 ns (300 ns for high-
speed mode). In master mode, the I
2
C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t
sr
(the time for SCL to go from low to V
IH
) exceeds
the time determined by the input clock of the I
2
C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table in
table 15.6.
Table 15.6 Permissible SCL Rise Time (t
sr
) Values
Time Indication
IICX
t
cyc
Indication
I
2
C Bus
Specification
(Max.)
φ =
5 MHz
φ =
8 MHz
φ =
10 MHz
φ = 16
MHz
0 7.5t
cyc
Normal mode 1000 ns 1000 ns 937 ns 750 ns 468 ns
High-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns
1 17.5t
cyc
Normal mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns
High-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns
6. The I
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
2
C bus interface SCL and SDA output timing is prescribed by t
Scyc
and t
cyc
, as
shown in table 15.5. However, because of the rise and fall times, the I
2
C bus interface
specifications may not be satisfied at the maximum transfer rate. Table 15.7 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times. The values in the above table will vary depending on the settings of the
IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to
achieve the maximum transfer rate; therefore, whether or not the I
2
C bus interface
specifications are met must be determined in accordance with the actual setting conditions.
t
BUFO
fails to meet the I
2
C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
2
C bus.
t
SCLLO
in high-speed mode and t
STASO
in standard mode fail to satisfy the I
2
C bus interface
specifications for worst-case calculations of t
Sr
/t
Sf
. Possible solutions that should be
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
2
C
bus.