Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 260 of 412
REJ09B0142-0600
15.4.7 IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 15.11 shows the IRIC set timing and SCL control.
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I
2
C bus format, no wait)
SCL
SDA
IRIC
User processing Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
1A
8
1
1
A
7
1897
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I
2
C bus format, wait inserted)
SCL
SDA
IRIC
User processing
Clear
IRIC
Clear
IRIC
Write to ICDR (transmit)
or read ICDR (receive)
SCL
SDA
IRIC
User processing
(c) When FS = 1 and FSX = 1 (synchronous serial format)
Clear IRIC Write to ICDR (transmit)
or read ICDR (receive)
8
89
8
7
1
8
7
1
Figure 15.11 IRIC Setting Timing and SCL Control