Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 256 of 412
REJ09B0142-0600
5. Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.
Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is
changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in
ICCR is cleared to 0.
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(master output)
Start condition issuance
SCL
(slave output)
Interrupt
request
generation
Address + R/W
Address + R/W
[5] ICDR read [5] IRIC clearance
User processing
Slave address
Data 1
[4]
A
R/W
High
Figure 15.7 Example of Slave Receive Mode Operation Timing (1)
(MLS = ACKB = 0)