Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 252 of 412
REJ09B0142-0600
9. Write the transmit data to ICDR. As indicating the end of the transfer, and so the IRIC flag is
cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in the step
[6]. Transmission of the next frame is performed in synchronization with the internal clock.
10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit
is 0). When there is data to be transmitted, go to the step [9] to continue next transmission.
When the slave device has not acknowledged (ACKB bit is set to 1), operate the step [12] to
end transmission.
12. Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from low
to high when SCL is high, and generates the stop condition.
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7
Slave address
Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
IRTR
ICDR
SCL
(master output)
Start condition generation
Data 1
Address + R/W
[4] Write BBSY = 1
and SCP = 0
(start condition
issuance)
[9] IRIC clearance
[9] ICDR write
[6] IRIC clearance
User processing
Slave address Data 1
R/W
[7]
[5]
A
[6] ICDR write
Normal
operation
ICDR writing
prohibited
Note: * Data write timing in ICDR
*
Figure 15.5 Master Transmit Mode Operation Timing Example
(MLS = WAIT = 0)