Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 249 of 412
REJ09B0142-0600
Table 15.4 Flags and Transfer States
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State
1/0 1/0 0 0 0 0 0 0 0 0 0 Idle state (flag clearing required)
1 1 0 0 0 0 0 0 0 0 0 Start condition issuance
1 1 1 0 0 1 0 0 0 0 0 Start condition established
1 1/0 1 0 0 0 0 0 0 0 0/1 Master mode wait
1 1/0 1 0 0 1 0 0 0 0 0/1 Master mode transmit/receive end
0 0 1 0 0 0 1/0 1 1/0 1/0 0 Arbitration lost
0 0 1 0 0 0 0 0 1 0 0 SAR match by first frame in slave
mode
0 0 1 0 0 0 0 0 1 1 0 General call address match
0 0 1 0 0 0 1 0 0 0 0 SARX match
0 1/0 1 0 0 0 0 0 0 0 0/1 Slave mode transmit/receive end
(except after SARX match)
0
0
1/0
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
Slave mode transmit/receive end
(after SARX match)
0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 Stop condition detected
15.4 Operation
The I
2
C bus interface has serial and I
2
C bus formats.
15.4.1 I
2
C Bus Data Format
The I
2
C bus formats are addressing formats and an acknowledge bit is inserted. These are shown
in figures 15.3. Figure 15.5 shows the I
2
C bus timing. The first frame following a start condition
always consists of 8 bits.