Datasheet
Section 15 I
2
C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 234 of 412
REJ09B0142-0600
Figure 15.1 shows a block diagram of the I
2
C bus interface.
Figure 15.2 shows an example of I/O pin connections to external circuits. The I/O pins are NMOS
open drains. Set the upper limit of voltage applied to the power supply (V
CC
) voltage range +
0.3 V, i.e. 5.8 V.
φ
PS
Noise
canceler
Noise
canceler
Clock
control
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
Address
comparator
SAR, SARX
Interrupt
generator
ICDRS
ICDRR
ICDRT
ICSR
ICMR
ICCR
Internal data bus
Interrupt
request
SCL
SDA
[Legend]
ICCR:
ICMR:
ICSR:
ICDR:
SAR:
SARX:
PS:
I
2
C bus control register
I
2
C bus mode register
I
2
C bus status register
I
2
C bus data register
Slave address register
Slave address register X
Prescaler
Figure 15.1 Block Diagram of I
2
C Bus Interface