Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 233 of 412
REJ09B0142-0600
Section 15 I
2
C Bus Interface (IIC)
The I
2
C bus interface conforms to and provides a subset of the Philips I
2
C bus (inter-IC bus)
interface functions. The register configuration that controls the I
2
C bus differs partly from the
Philips configuration, however.
15.1 Features
• Selection of I
2
C format or clocked synchronous serial format
 I
2
C bus format: addressing format with acknowledge bit, for master/slave operation
 Clocked synchronous serial format: non-addressing format without acknowledge bit, for
master operation only
• I
2
C bus format
• Two ways of setting slave address
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Wait function in master mode
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
• Wait function in slave mode
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three interrupt sources
 Data transfer end (including transmission mode transition with I
2
C bus format and address
reception after loss of master arbitration)
 Address match: when any slave address matches or the general call address is received in
slave receive mode
 Stop condition detection
• Selection of 16 internal clocks (in master mode)
• Direct bus drive
 Two pins, SCL and SDA pins function as NMOS open-drain outputs when the bus drive
function is selected.