Datasheet

Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 232 of 412
REJ09B0142-0600
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Internal basic
clock
16 clocks
8 clocks
Receive data
(RxD)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 00
7
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode