Datasheet

Section 9 I/O Ports
Rev. 6.00 Mar. 24, 2006 Page 127 of 412
REJ09B0142-0600
9.3.3 Port Data Register 5 (PDR5)
PDR5 is a general I/O port data register of port 5.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P57
P56
P55
P54
P53
P52
P51
P50
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stores output data for port 5 pins.
If PDR5 is read while PCR5 bits are set to 1, the value
stored in PDR5 are read. If PDR5 is read while PCR5
bits are cleared to 0, the pin states are read regardless
of the value stored in PDR5.
Note: Do not set P57 and P56 to 1 for H8/3664N.
9.3.4 Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit Bit Name
Initial
Value R/W Description
7
6


0
0


Reserved
These bits are always read as 0.
5
4
3
2
1
0
PUCR55
PUCR54
PUCR53
PUCR52
PUCR51
PUCR50
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Only bits for which PCR5 is cleared are valid. The pull-
up MOS of the corresponding pins enter the on-state
when these bits are set to 1, while they enter the off-
state when these bits are cleared to 0.