Datasheet

Rev. 6.00 Mar. 24, 2006 Page xiii of xxviii
11.2 Input/Output Pins.............................................................................................................. 147
11.3 Register Descriptions........................................................................................................ 147
11.3.1 Timer Counter V (TCNTV).............................................................................. 147
11.3.2 Time Constant Registers A and B (TCORA, TCORB) .................................... 148
11.3.3 Timer Control Register V0 (TCRV0)............................................................... 148
11.3.4 Timer Control/Status Register V (TCSRV)...................................................... 150
11.3.5 Timer Control Register V1 (TCRV1)............................................................... 151
11.4 Operation .......................................................................................................................... 152
11.4.1 Timer V Operation............................................................................................ 152
11.5 Timer V Application Examples ........................................................................................ 155
11.5.1 Pulse Output with Arbitrary Duty Cycle........................................................... 155
11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .......... 156
11.6 Usage Notes...................................................................................................................... 157
Section 12 Timer W...........................................................................................159
12.1 Features............................................................................................................................. 159
12.2 Input/Output Pins.............................................................................................................. 162
12.3 Register Descriptions........................................................................................................ 162
12.3.1 Timer Mode Register W (TMRW) ................................................................... 163
12.3.2 Timer Control Register W (TCRW) ................................................................. 164
12.3.3 Timer Interrupt Enable Register W (TIERW) .................................................. 165
12.3.4 Timer Status Register W (TSRW) .................................................................... 166
12.3.5 Timer I/O Control Register 0 (TIOR0)............................................................. 167
12.3.6 Timer I/O Control Register 1 (TIOR1)............................................................. 169
12.3.7 Timer Counter (TCNT)..................................................................................... 170
12.3.8 General Registers A to D (GRA to GRD)......................................................... 171
12.4 Operation .......................................................................................................................... 172
12.4.1 Normal Operation ............................................................................................. 172
12.4.2 PWM Operation................................................................................................ 176
12.5 Operation Timing.............................................................................................................. 181
12.5.1 TCNT Count Timing ........................................................................................ 181
12.5.2 Output Compare Output Timing....................................................................... 182
12.5.3 Input Capture Timing........................................................................................ 183
12.5.4 Timing of Counter Clearing by Compare Match.............................................. 183
12.5.5 Buffer Operation Timing .................................................................................. 184
12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match..............................185
12.5.7 Timing of IMFA to IMFD Setting at Input Capture ......................................... 186
12.5.8 Timing of Status Flag Clearing......................................................................... 186
12.6 Usage Notes...................................................................................................................... 187