Datasheet

Section 9 I/O Ports
Rev. 6.00 Mar. 24, 2006 Page 118 of 412
REJ09B0142-0600
9.1.3 Port Data Register 1 (PDR1)
PDR1 is a general I/O port data register of port 1.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P17
P16
P15
P14

P12
P11
P10
0
0
0
0
1
0
0
0
R/W
R/W
R/W
R/W

R/W
R/W
R/W
PDR1 stores output data for port 1 pins.
If PDR1 is read while PCR1 bits are set to 1, the value
stored in PDR1 are read. If PDR1 is read while PCR1
bits are cleared to 0, the pin states are read regardless
of the value stored in PDR1.
Bit 3 is a reserved bit. This bit is always read as 1.
9.1.4 Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PUCR17
PUCR16
PUCR15
PUCR14

PUCR12
PUCR11
PUCR10
0
0
0
0
1
0
0
0
R/W
R/W
R/W
R/W

R/W
R/W
R/W
Only bits for which PCR1 is cleared are valid. The pull-
up MOS of P17 to P14 and P12 to P10 pins enter the
on-state when these bits are set to 1, while they enter
the off-state when these bits are cleared to 0.
Bit 3 is a reserved bit. This bit is always read as 1.