Datasheet

Section 6 Power-Down Modes
Rev. 6.00 Mar. 24, 2006 Page 84 of 412
REJ09B0142-0600
6.1 Register Descriptions
The registers related to power-down modes are listed below.
• System control register 1 (SYSCR1)
• System control register 2 (SYSCR2)
• Module standby control register 1 (MSTCR1)
6.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit Bit Name
Initial
Value R/W Description
7 SSBY 0 R/W Software Standby
This bit selects the mode to transit after the execution
of the SLEEP instruction.
0: a transition is made to sleep mode or subsleep
mode.
1: a transition is made to standby mode.
For details, see table 6.2.
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
These bits designate the time the CPU and peripheral
modules wait for stable clock operation after exiting
from standby mode, subactive mode, or subsleep mode
to active mode or sleep mode due to an interrupt. The
designation should be made according to the clock
frequency so that the waiting time is at least 6.5 ms.
The relationship between the specified value and the
number of wait states is shown in table 6.1. When an
external clock is to be used, the minimum value (STS2
= STS1 = STS0 = 1) is recommended.