Datasheet

Rev. 6.00 Mar. 24, 2006 Page ix of xxviii
Contents
Section 1 Overview................................................................................................1
1.1 Features................................................................................................................................. 1
1.2 Internal Block Diagram.........................................................................................................3
1.3 Pin Arrangement................................................................................................................... 5
1.4 Pin Functions ........................................................................................................................ 9
Section 2 CPU......................................................................................................13
2.1 Address Space and Memory Map....................................................................................... 14
2.2 Register Configuration........................................................................................................ 17
2.2.1 General Registers................................................................................................ 18
2.2.2 Program Counter (PC) ........................................................................................ 19
2.2.3 Condition-Code Register (CCR)......................................................................... 19
2.3 Data Formats....................................................................................................................... 21
2.3.1 General Register Data Formats........................................................................... 21
2.3.2 Memory Data Formats........................................................................................ 23
2.4 Instruction Set..................................................................................................................... 24
2.4.1 Table of Instructions Classified by Function ...................................................... 24
2.4.2 Basic Instruction Formats ................................................................................... 34
2.5 Addressing Modes and Effective Address Calculation....................................................... 35
2.5.1 Addressing Modes .............................................................................................. 35
2.5.2 Effective Address Calculation ............................................................................ 39
2.6 Basic Bus Cycle.................................................................................................................. 41
2.6.1 Access to On-Chip Memory (RAM, ROM)........................................................ 41
2.6.2 On-Chip Peripheral Modules .............................................................................. 42
2.7 CPU States..........................................................................................................................43
2.8 Usage Notes........................................................................................................................ 44
2.8.1 Notes on Data Access to Empty Areas ............................................................... 44
2.8.2 EEPMOV Instruction.......................................................................................... 44
2.8.3 Bit Manipulation Instruction............................................................................... 45
Section 3 Exception Handling .............................................................................51
3.1 Exception Sources and Vector Address.............................................................................. 51
3.2 Register Descriptions.......................................................................................................... 53
3.2.1 Interrupt Edge Select Register 1 (IEGR1) ..........................................................53
3.2.2 Interrupt Edge Select Register 2 (IEGR2) ..........................................................54
3.2.3 Interrupt Enable Register 1 (IENR1) .................................................................. 55