To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3664 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/3664N H8/3664F H8/3664 H8/3663 H8/3662 H8/3661 H8/3660 HD64N3664 HD64F3664 HD6433664 HD6433663 HD6433662 HD6433661 HD6433660 Rev.6.00 2006.
Rev. 6.00 Mar.
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8/3664 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/3664 Group in the design of application systems.
5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break control registers must not be accessed. 6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and P87 are input pins, and P86 is an output pin. Related Manuals: The latest versions of all related manuals are available from our web site.
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Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features................................................................................................................................. 1 Internal Block Diagram......................................................................................................... 3 Pin Arrangement ....................................................................................
3.3 3.4 3.5 3.2.4 Interrupt Flag Register 1 (IRR1)......................................................................... 56 3.2.5 Wakeup Interrupt Flag Register (IWPR) ............................................................ 57 Reset Exception Handling .................................................................................................. 59 Interrupt Exception Handling ............................................................................................. 59 3.4.
6.2 6.3 6.4 6.5 6.6 6.1.2 System Control Register 2 (SYSCR2) ................................................................ 86 6.1.3 Module Standby Control Register 1 (MSTCR1) ................................................ 87 Mode Transitions and States of LSI.................................................................................... 88 6.2.1 Sleep Mode ......................................................................................................... 91 6.2.2 Standby Mode ............
9.2 9.3 9.4 9.5 9.6 9.1.1 Port Mode Register 1 (PMR1) .......................................................................... 116 9.1.2 Port Control Register 1 (PCR1) ........................................................................ 117 9.1.3 Port Data Register 1 (PDR1) ............................................................................ 118 9.1.4 Port Pull-Up Control Register 1 (PUCR1)........................................................ 118 9.1.5 Pin Functions ...................
11.2 11.3 11.4 11.5 11.6 Input/Output Pins.............................................................................................................. 147 Register Descriptions........................................................................................................ 147 11.3.1 Timer Counter V (TCNTV) .............................................................................. 147 11.3.2 Time Constant Registers A and B (TCORA, TCORB) .................................... 148 11.3.
Section 13 Watchdog Timer.............................................................................. 191 13.1 13.2 13.3 Features............................................................................................................................. 191 Register Descriptions........................................................................................................ 191 13.2.1 Timer Control/Status Register WD (TCSRWD) .............................................. 192 13.2.
14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................... 231 Section 15 I2C Bus Interface (IIC) .....................................................................233 15.1 15.2 15.3 15.4 15.5 Features............................................................................................................................. 233 Input/Output Pins...................................................
16.6.1 16.6.2 Permissible Signal Source Impedance .............................................................. 286 Influences on Absolute Accuracy ..................................................................... 286 Section 17 EEPROM......................................................................................... 287 17.1 17.2 17.3 17.4 17.5 Features.............................................................................................................................
20.3 20.4 20.5 20.2.6 Memory Characteristics .................................................................................... 326 20.2.7 EEPROM Characteristics.................................................................................. 328 Electrical Characteristics (Mask ROM Version) .............................................................. 329 20.3.1 Power Supply Voltage and Operating Ranges .................................................. 329 20.3.2 DC Characteristics .................
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Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Overview Internal Block Diagram of H8/3664 of F-ZTATTM and Mask-ROM Versions ............. 3 Internal Block Diagram of H8/3664N of F-ZTATTM Version with EEPROM ............. 4 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions (FP-64E, FP-64A)......................................................................................................... 5 Figure 1.4 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions (FP-48F, FP-48B) ..........
Figure 4.2 Figure 4.2 Figure 4.3 Figure 4.4 Address Break Interrupt Operation Example (1)......................................................... 71 Address Break Interrupt Operation Example (2)......................................................... 72 Operation when Condition is not Satisfied in Branch Instruction ............................... 73 Operation when Another Interrupt is Accepted at Address Break Setting Instruction ..........................................................................
Figure 11.2 Increment Timing with Internal Clock .................................................................... 153 Figure 11.3 Increment Timing with External Clock ................................................................... 153 Figure 11.4 OVF Set Timing ...................................................................................................... 153 Figure 11.5 CMFA and CMFB Set Timing ................................................................................ 154 Figure 11.
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the Same Timing .................................................................................... 189 Section 13 Watchdog Timer Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 191 Figure 13.2 Watchdog Timer Operation Example...................................................................... 195 Section 14 Figure 14.1 Figure 14.2 Figure 14.
Figure 15.6 Master Receive Mode Operation Timing Example (1) (MLS = ACKB = 0, WAIT = 1) ............................................................................. 254 Figure 15.6 Master Receive Mode Operation Timing Example (2) (MLS = ACKB = 0, WAIT = 1) ............................................................................. 255 Figure 15.7 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) ....... 256 Figure 15.
Section 20 Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 Figure 20.5 Figure 20.6 Figure 20.7 Figure 20.8 Electrical Characteristics System Clock Input Timing .................................................................................... 343 RES Low Width Timing.......................................................................................... 343 Input Timing............................................................................................................
Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 24 Table 2.2 Data Transfer Instructions....................................................................................... 25 Table 2.3 Arithmetic Operations Instructions (1) ...............................
Table 7.4 Table 7.5 Table 7.6 Table 7.7 Reprogram Data Computation Table .................................................................... 106 Additional-Program Data Computation Table ...................................................... 106 Programming Time ............................................................................................... 106 Flash Memory Operating States............................................................................ 111 Section 10 Timer A Table 10.
Section 20 Electrical Characteristics Table 20.1 Absolute Maximum Ratings ................................................................................. 311 Table 20.2 DC Characteristics (1)........................................................................................... 314 Table 20.2 DC Characteristics (2)........................................................................................... 318 Table 20.2 DC Characteristics (3).............................................................
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Section 1 Overview Section 1 Overview 1.
Section 1 Overview • Supports various power-down modes Note: F-ZTATTM is a trademark of Renesas Technology Corp. • Compact package Package Code Body Size Pin Pitch LQFP-64 FP-64E 10.0 × 10.0 mm 0.5 mm QFP-64 FP-64A 14.0 × 14.0 mm 0.8 mm LQFP-48 FP-48F 10.0 × 10.0 mm 0.65 mm LQFP-48 FP-48B 7.0 × 7.0 mm 0.5 mm SDIP-42 DP-42S 14.0 × 37.3 mm 1.78 mm Only LQFP-64 (FP-64E) for H8/3664N package Rev. 6.00 Mar.
Section 1 Overview Port 8 Port 7 P74/TMRIV P75/TMCIV P76/TMOV Port 5 P20/SCK3 P21/RXD P22/TXD P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5/ADTRG P56/SDA P57/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 CPU H8/300H Port 1 Data bus (lower) Port 2 P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV System clock generator Port B Subclock generator OSC1 OSC2 X1 X2 NMI TEST RES VCL Internal Bloc
Port 8 Port 7 SCL P74/TMRIV P75/TMCIV P76/TMOV P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5/ADTRG PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 Port 1 I2C bus SDA P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 Port 5 P20/SCK3 P21/RXD P22/TXD CPU H8/300H Data bus (lower) Port 2 P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV System clock generator Port B Subclock generator OSC1 OSC2 X1 X2 NMI TEST RES VCL VSS VCC Section 1 Overview
Section 1 Overview NC NC NMI P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 P20/SCK3 P21/RXD P22/TXD NC Pin Arrangement NC 1.
NMI P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 P20/SCK3 P21/RXD P22/TXD Section 1 Overview 36 35 34 33 32 31 30 29 28 27 26 25 40 21 P57/SCL PB4/AN4 41 20 P56/SDA PB5/AN5 42 H8/3664 19 P12 PB6/AN6 43 Top View 18 P11 PB7/AN7 44 17 P10/TMOW PB3/AN3 45 16 P55/WKP5/ADTRG PB2/AN2 46 15 P54/WKP4 PB1/AN1 47 14 P53/WKP3 PB0/AN0 48 13 P52/WKP2 4 5 6 7 8 9 10 11 12 P51/WKP1 3 P50/WKP0 2 Vcc 1 OSC1 P74/TMRIV P17/IRQ3/TRGV OSC2 22 VSS
Section 1 Overview PB3/AN3 1 42 P17/IRQ3/TRGV PB2/AN2 2 41 P16/IRQ2 PB1/AN1 3 40 P15/IRQ1 PB0/AN0 4 39 P14/IRQ0 AVCC 5 38 P22/TXD X2 6 37 P21/RXD X1 7 36 P20/SCK3 VCL 8 35 P87 RES 9 34 P86 TEST 10 H8/3664 33 P85 VSS 11 Top view 32 P84/FTIOD OSC2 12 31 P83/FTIOC OSC1 13 30 P82/FTIOB VCC 14 29 P81/FTIOA P50/WKP0 15 28 P80/FTCI P51/WKP1 16 27 NMI P52/WKP2 17 26 P76/TMOV P53/WKP3 18 25 P75/TMCIV P54/WKP4 19 24 P74/TMRIV P55/WKP5/ADTR
NC NC NMI P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 P20/SCK3 P21/RXD P22/TXD NC NC Section 1 Overview 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 29 P75/TMCIV P16/IRQ2 53 28 P74/TMRIV P17/IRQ3/TRGV 54 27 SCL* PB4/AN4 55 26 SDA* PB5/AN5 56 25 P12 PB6/AN6 57 H8/3664N 24 P11 PB7/AN7 58 Top View 23 P10/TMOW PB3/AN3 59 22 P55/WKP5/ADTRG PB2/AN2 60 21 P54/WKP4 PB1/AN1 61 20 P53/WKP3 PB0/AN0 62 19 P52/WKP2 NC 63 18 NC NC
Section 1 Overview 1.4 Table 1.1 Pin Functions Pin Functions Pin No. H8/3664 Type Symbol Power source VCC H8/3664N FP-64E, FP-48F, FP-64A FP-48B DP-42S FP-64E I/O Functions 12 10 14 12 Input Power supply pin. Connect this pin to the pins system power supply. VSS 9 7 11 9 Input Ground pin. Connect all these pins to the system power supply (0V). AVCC 3 1 5 3 Input Analog power supply pin for the A/D converter.
Section 1 Overview Pin No. H8/3664 H8/3664N FP-64E, FP-48F, Type Symbol FP-64A FP-48B DP-42S FP-64E I/O Functions Interrupt pins NMI 35 25 27 35 Input Non-maskable interrupt request input pin. Be sure to pull-up by a pull-up resistor. IRQ0 to 51 to 54 37 to 40 39 to 42 51 to 54 Input IRQ3 External interrupt request input pins. Can select the rising or falling edge.
Section 1 Overview Pin No.
Section 1 Overview Rev. 6.00 Mar.
Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added.
Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map.
Section 2 CPU HD6433662 (Mask ROM version) H'0000 H'0033 H'0034 Interrupt vector HD6433663 (Mask ROM version) H'0000 H'0033 H'0034 HD6433664 (Mask ROM version) H'0000 H'0033 H'0034 Interrupt vector Interrupt vector On-chip ROM (16 kbytes) On-chip ROM (24 kbytes) H'3FFF On-chip ROM (32 kbytes) H'5FFF H'7FFF Not used Not used Not used H'FB80 H'FD80 H'FF7F H'FF80 On-chip RAM (1 kbyte) On-chip RAM (1 kbyte) On-chip RAM (512 bytes) H'FF7F H'FF80 Internal I/O register H'FFFF H'FB80 H'FF7F H'F
Section 2 CPU HD64N3664 (On-chip EEPROM module) H'0000 User area (512 bytes) H'01FF Not used H'FF09 Slave address register Not used Figure 2.1 Memory Map (3) Rev. 6.00 Mar.
Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR).
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
Section 2 CPU Bit Initial Bit Name Value R/W 7 I R/W 1 Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 6.00 Mar.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.
Section 2 CPU Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) → Rd, Cannot be used in this LSI. MOVTPE B Rs → (EAs) Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.8 Instruction System Control Instructions Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd), EXR → (EAd) Transfers the CCR contents to a destination location.
Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. Rev. 6.00 Mar.
Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.7 shows examples of instruction formats. • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand.
Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.
Section 2 CPU (1) Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory.
Section 2 CPU (5) Absolute Address—@aa:8, @aa:16, @aa:24 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space.
Section 2 CPU (8) Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode.
Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states.
Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 19.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size.
Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. In the program halt state there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes.
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
Section 2 CPU 2.8.3 Bit Manipulation Instruction The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address or when a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated.
Section 2 CPU Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below.
Section 2 CPU As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. Prior to executing BSET MOV.B MOV.B MOV.B #80, R0L, R0L, R0L @RAM0 @PDR5 The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5.
Section 2 CPU (2) Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin.
Section 2 CPU As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PDR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PDR5. Prior to executing BCLR MOV.B MOV.B MOV.
Section 2 CPU Rev. 6.00 Mar.
Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.
Section 3 Exception Handling Table 3.
Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. • • • • • Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt flag register 1 (IRR1) Wakeup interrupt flag register (IWPR) 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to IRQ0.
Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Bit Bit Name Initial Value R/W Description 7 1 Reserved 6 1 These bits are always read as 1.
Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts. Bit Bit Name Initial Value R/W Description 7 IENDT 0 R/W Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 IENTA 0 R/W Timer A Interrupt Enable When this bit is set to 1, timer A overflow interrupt requests are enabled.
Section 3 Exception Handling 3.2.4 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3 to IRQ0 interrupt requests. Bit Bit Name Initial Value R/W Description 7 IRRDT 0 R/W 6 IRRTA 0 R/W 5 4 3 IRRI3 1 1 0 R/W 2 IRRI2 0 R/W 1 IRRI1 0 R/W Direct Transfer Interrupt Request Flag [Setting condition] When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 0 IRRl0 0 R/W IRQ0 Interrupt Request Flag [Setting condition] When IRQ0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI0 is cleared by writing 0 3.2.5 Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 2 IWPF2 0 R/W WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF2 is cleared by writing 0. 1 IWPF1 0 R/W WKP1 Interrupt Request Flag [Setting condition] When WKP1 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF1 is cleared by writing 0.
Section 3 Exception Handling 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock cycles.
Section 3 Exception Handling (3) WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2.
Section 3 Exception Handling 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For timer A interrupt requests and direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1 and IENR1. When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt.
Section 3 Exception Handling SP – 4 SP (R7) CCR SP – 3 SP + 1 CCR*3 SP – 2 SP + 2 PCH SP – 1 SP + 3 PCL SP (R7) SP + 4 Even address Stack area Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling [Legend] PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1.
(2) (1) (4) (3) Internal processing (1) (5) (7) (6) Stack access (9) Vector fetch (8) (10) (9) Prefetch instruction of Internal interrupt-handling routine processing (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.
Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Section 3 Exception Handling CCR I bit ← 1 Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) Set port mode register bit Execute NOP instruction After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0 Clear interrupt request flag to 0 CCR I bit ← 0 Interrupt mask cleared Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure Rev. 6.
Section 3 Exception Handling Rev. 6.00 Mar.
Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Section 4 Address Break 4.1 Register Descriptions Address break has the following registers. • • • • Address break control register (ABRKCR) Address break status register (ABRKSR) Break address register (BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions.
Section 4 Address Break Bit Bit Name Initial Value R/W Description 1 DCMP1 0 R/W Data Compare Condition Select 1 and 0 0 DCMP0 0 R/W These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data bus 10: Compares upper 8-bit data between BDRH and data bus 11: Compares 16-bit data between BDR and data bus [Legend] X: Don't care.
Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Bit Bit Name Initial Value R/W Description 7 ABIF 0 R/W Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR is satisfied [Clearing condition] When 0 is written after ABIF=1 is read 6 ABIE 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled.
Section 4 Address Break 4.2 Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked because of the I bit in CCR of the CPU. Figures 4.
Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked.
Section 4 Address Break 4.3 Usage Notes When an address break is set to an instruction after a conditional branch instruction, and the instruction set when the condition of the branch instruction is not satisfied is executed (see figure 4.3), note that an address break interrupt request is not generated. Therefore an address break must not be set to the instruction after a conditional branch instruction. [Register setting] [Program] ABRKCR = H'80 BAR = H'0136 012A MOV.B . . .
Section 4 Address Break When another interrupt request is accepted before an instruction to which an address break is set is executed, exception handling of an address break interrupt is not executed. However, the ABIF bit is set to 1 (see figure 4.4). Therefore the ABIF bit must be read during exception handling of an address break interrupt. [Register setting] ABRKCR = H'80 BAR = H'0144 External interrupt MOV [Program] 001C : 0142 * 0144 0146 0900 : MOV.B #H'23,R1H MOV.B #H'45,R1H MOV.
Section 4 Address Break When an address break is set to an instruction as a branch destination of a conditional branch instruction, the instruction set when the condition of the branch instruction is not satisfied is not executed, and an address break is generated. Therefore an address break must not be set to the instruction as a branch destination of a conditional branch instruction. [Register setting] • ADBRKCR = H'80 • BAR = H'0150 [Program] 0134 BNE 0136 NOP 0138 NOP * 0150 MOV.B . . .
Section 4 Address Break Rev. 6.00 Mar.
Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. Figure 5.1 shows a block diagram of the clock pulse generators.
Section 5 Clock Pulse Generators 5.1 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system clock generator. OSC 2 LPM OSC 1 LPM: Low-power mode (standby mode, subactive mode, subsleep mode) Figure 5.2 Block Diagram of System Clock Generator 5.1.1 Connecting Crystal Resonator Figure 5.
Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters Frequency (MHz) 2 4 8 10 16 RS (max) 500 Ω 120 Ω 80 Ω 60 Ω 50 Ω C0 (max) 7 pF 7 pF 7 pF 7 pF 7 pF 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. C1 OSC1 C2 C1 = 30 pF ±10% C2 = 30 pF ±10% OSC2 Note: Capacitances are reference values. Figure 5.5 Typical Connection to Ceramic Resonator 5.1.
Section 5 Clock Pulse Generators 5.2 Subclock Generator Figure 5.7 shows a block diagram of the subclock generator. x2 8MΩ x1 Note : Resistance is a reference value. Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.8. Figure 5.9 shows the equivalent circuit of the 32.768-kHz crystal resonator. C1 X1 C2 X2 C1 = C2 = 15 pF (typ.
Section 5 Clock Pulse Generators 5.2.2 Pin Connection when Not Using Subclock When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown in figure 5.10. VCL or VSS X1 X2 Open Figure 5.10 Pin Connection when not Using Subclock 5.3 Prescalers 5.3.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once per clock period.
Section 5 Clock Pulse Generators 5.4 Usage Notes 5.4.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator element manufacturer.
Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. • Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. • System control register 1 (SYSCR1) • System control register 2 (SYSCR2) • Module standby control register 1 (MSTCR1) 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W Software Standby This bit selects the mode to transit after the execution of the SLEEP instruction.
Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 3 NESEL 0 R/W Noise Elimination Sampling Frequency Select The subclock pulse generator generates the watch clock signal (φW) and the system clock pulse generator generates the oscillator clock (φOSC). This bit selects the sampling frequency of the oscillator clock when the watch clock signal (φW) is sampled. When φOSC = 4 to 16 MHz, clear NESEL to 0.
Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value R/W Description 7 SMSEL 0 R/W Sleep Mode Selection 6 LSON 0 R/W Low Speed on Flag 5 DTON 0 R/W Direct Transfer on Flag These bits select the mode to transit after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2.
Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0.
Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program.
Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling DTON SSBY SMSEL LSON Transition Mode after SLEEP Instruction Execution 0 0 0 0 Sleep mode 1 1 0 Active mode Subactive mode Subsleep mode 1 1 Transition Mode due to Interrupt Active mode Subactive mode 1 X X Standby mode Active mode X 0* 0 Active mode (direct transition) — X X 1 Subactive mode (direct transition) — [Legend] X: Don't care.
Section 6 Power-Down Modes Table 6.
Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register.
Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, operation of the CPU and on-chip peripheral modules other than timer A is halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts.
Section 6 Power-Down Modes 6.3 Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. 6.4 Direct Transition The CPU can execute programs in two modes: active and subactive mode. A direct transition is a transition between these two modes without stopping program execution.
Section 6 Power-Down Modes 6.4.2 Direct Transition from Subactive Mode to Active Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2).
Section 7 ROM Section 7 ROM The features of the 32-kbyte flash memory built into the flash memory version are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 kbyte × 4 blocks and 28 kbytes × 1 block. To erase the entire flash memory, each block must be erased in turn. • Reprogramming capability The flash memory can be reprogrammed up to 1,000 times.
Section 7 ROM 7.1 Block Configuration Figure 7.1 shows the block configuration of 32-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 1 kbyte × 4 blocks and 28 kbytes × 1 block. Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. • • • • • Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode.
Section 7 ROM Bit Bit Name Initial Value R/W Description 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, program-verify mode is cancelled.
Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. Bit Bit Name Initial Value R/W 7 to 5 — All 0 — Description Reserved These bits are always read as 0. 4 EB4 0 R/W When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF will be erased.
Section 7 ROM 7.2.5 Flash Memory Enable Register (FENR) Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1, and FLPWCR. Bit Bit Name Initial Value R/W Description 7 FLSHE 0 R/W Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 — All 0 — Reserved These bits are always read as 0. 7.
Section 7 ROM 7.3.1 Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3.
Section 7 ROM Boot Mode Operation Host Operation Communication Contents Processing Contents Boot mode initiation Item Table 7.2 Branches to boot program at reset-start. Boot program initiation Flash memory erase Bit rate adjustment Continuously transmits data H'00 at specified bit rate. Transfer of number of bytes of programming control program LSI Operation Processing Contents Transmits data H'55 when data H'00 is received error-free. H'00, H'00 . . .
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 MHz 9,600 bps 8 to 16 MHz 4,800 bps 4 to 16 MHz 2,400 bps 2 to 16 MHz 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program.
Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 — 1 1 1 Remains in erased state Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Additional-Program Data Comments 0 0 0 Additional-program bit 0 1 1 No additional programming 1 0 1 No additional programming 1 1 1 No additional programming Comments Table 7.
Section 7 ROM 7.4.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 10 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs * n←n+1 Read verify data No Verify data + all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erase block erased ? n ≤100 ? Yes No Yes SWE bit ← 0 SWE bit ← 0
Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode.
Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset. 7.
Section 7 ROM Table 7.7 Flash Memory Operating States Flash Memory Operating State LSI Operating State PDWND = 0 (Initial value) PDWND = 1 Active mode Normal operating mode Normal operating mode Subactive mode Power-down mode Normal operating mode Sleep mode Normal operating mode Normal operating mode Subsleep mode Standby mode Standby mode Standby mode Standby mode Standby mode Rev. 6.00 Mar.
Section 7 ROM Rev. 6.00 Mar.
Section 8 RAM Section 8 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Section 8 RAM Rev. 6.00 Mar.
Section 9 I/O Ports Section 9 I/O Ports The group of this LSI has twenty-nine general I/O ports (twenty-seven ports for H8/3664N) and eight general input-only ports. Port 8 is a large current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset.
Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description 7 IRQ3 0 R/W P17/IRQ3/TRGV Pin Function Switch This bit selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6 IRQ2 0 R/W P16/IRQ2 Pin Function Switch This bit selects whether pin P16/IRQ2 is used as P16 or as IRQ2.
Section 9 I/O Ports Bit Bit Name Initial Value R/W Description 0 TMOW 0 R/W P10/TMOW Pin Function Switch This bit selects whether pin P10/TMOW is used as P10 or as TMOW. 0: General I/O port 1: TMOW output pin 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Section 9 I/O Ports 9.1.3 Port Data Register 1 (PDR1) PDR1 is a general I/O port data register of port 1. Bit Bit Name Initial Value R/W Description 7 P17 0 R/W PDR1 stores output data for port 1 pins. 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W If PDR1 is read while PCR1 bits are set to 1, the value stored in PDR1 are read. If PDR1 is read while PCR1 bits are cleared to 0, the pin states are read regardless of the value stored in PDR1. 3 1 Bit 3 is a reserved bit.
Section 9 I/O Ports 9.1.5 Pin Functions The correspondence between the register specification and the port functions is shown below. • P17/IRQ3/TRGV Pin Register PMR1 PCR1 Bit Name IRQ3 PCR17 Pin Function 0 P17 input pin 1 P17 output pin X IRQ3 input/TRGV input pin Setting value 0 1 [Legend] X: Don't care. • P16/IRQ2 Pin Register PMR1 PCR1 Bit Name IRQ2 PCR16 Pin Function 0 P16 input pin 1 P16 output pin X IRQ2 input pin Setting value 0 1 [Legend] X: Don't care.
Section 9 I/O Ports • P14/IRQ0 Pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function 0 P14 input pin 1 P14 output pin X IRQ0 input pin Setting value 0 1 [Legend] X: Don't care.
Section 9 I/O Ports 9.2 Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses. P22/TXD P21/RXD Port 2 P20/SCK3 Figure 9.2 Port 2 Pin Configuration Port 2 has the following registers. • Port control register 2 (PCR2) • Port data register 2 (PDR2) 9.2.
Section 9 I/O Ports 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Bit Bit Name Initial Value R/W Description 7 1 Reserved 6 1 These bits are always read as 1. 5 1 4 1 3 1 2 P22 0 R/W PDR2 stores output data for port 2 pins. 1 P21 0 R/W 0 P20 0 R/W PDR2 is read while PCR2 bits are set to 1, the value stored in PDR2 is read.
Section 9 I/O Ports • P21/RXD Pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function 0 P21 input pin 1 P21 output pin X RXD input pin Setting Value 0 1 [Legend] X: Don't care. • P20/SCK3 Pin Register Bit Name SCR3 CKE1 Setting Value 0 SMR PCR2 CKE0 COM PCR20 Pin Function 0 0 0 P20 input pin 1 P20 output pin 0 0 1 X SCK3 output pin 0 1 X X SCK3 output pin 1 X X X SCK3 input pin [Legend] X: Don't care. Rev. 6.00 Mar.
Section 9 I/O Ports 9.3 Port 5 Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin, an A/D trigger input pin, wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting of the I2C bus interface register has priority for functions of the pins P57/SCL and P56/SDA.
Section 9 I/O Ports 9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W Description 7 0 Reserved 6 0 These bits are always read as 0. 5 WKP5 0 R/W P55/WKP5/ADTRG Pin Function Switch Selects whether pin P55/WKP5/ADTRG is used as P55 or as WKP5/ADTRG input. 0: General I/O port 1: WKP5/ADTRG input pin 4 WKP4 0 R/W P54/WKP4 Pin Function Switch Selects whether pin P54/WKP4 is used as P54 or as WKP4.
Section 9 I/O Ports Bit Bit Name Initial Value R/W Description 0 WKP0 0 R/W P50/WKP0 Pin Function Switch Selects whether pin P50/WKP0 is used as P50 or as WKP0. 0: General I/O port 1: WKP0 input pin 9.3.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5.
Section 9 I/O Ports 9.3.3 Port Data Register 5 (PDR5) PDR5 is a general I/O port data register of port 5. Bit Bit Name Initial Value R/W Description 7 P57 0 R/W Stores output data for port 5 pins. 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W If PDR5 is read while PCR5 bits are set to 1, the value stored in PDR5 are read. If PDR5 is read while PCR5 bits are cleared to 0, the pin states are read regardless of the value stored in PDR5.
Section 9 I/O Ports 9.3.5 Pin Functions The correspondence between the register specification and the port functions is shown below. • P57/SCL Pin Register ICCR PCR5 Bit Name ICE PCR57 Pin Function 0 P57 input pin 1 P57 output pin X SCL I/O pin Setting Value 0 1 [Legend] X: Don't care. SCL performs the NMOS open-drain output, that enables a direct bus drive.
Section 9 I/O Ports • P54/WKP4 Pin Register PMR5 PCR5 Bit Name WKP4 PCR54 Pin Function 0 P54 input pin 1 P54 output pin X WKP4 input pin Setting Value 0 1 [Legend] X: Don't care. • P53/WKP3 Pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Pin Function 0 P53 input pin 1 P53 output pin X WKP3 input pin Setting Value 0 1 [Legend] X: Don't care.
Section 9 I/O Ports • P51/WKP1 Pin Register PMR5 PCR5 Bit Name WKP1 PCR51 Pin Function 0 P51 input pin 1 P51 output pin X WKP1 input pin Setting Value 0 1 [Legend] X: Don't care. • P50/WKP0 Pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Pin Function 0 P50 input pin Setting Value 0 1 1 P50 output pin X WKP0 input pin [Legend] X: Don't care. 9.4 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4.
Section 9 I/O Ports Port 7 has the following registers. • Port control register 7 (PCR7) • Port data register 7 (PDR7) 9.4.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Bit Bit Name Initial Value R/W Description 7 Reserved 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W Setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.4.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P76/TMOV Pin Register TCSRV PCR7 Bit Name OS3 to OS0 PCR76 Pin Function 0 P76 input pin 1 P76 output pin X TMOV output pin Setting Value 0000 Other than the above values [Legend] X: Don't care.
Section 9 I/O Ports 9.5 Port 8 Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W has priority for functions of the pins P84/FTIOD, P83/FTIOC, P82/FTIOB, and P81/FTIOA. P80/FTCI also functions as a timer W input port that is connected to the timer W regardless of the register setting of port 8. P87 P86 P85 Port 8 P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI Figure 9.
Section 9 I/O Ports 9.5.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Bit Bit Name Initial Value R/W Description 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W When each of the port 8 pins P87 to P80 functions as an general I/O port, setting a PCR8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.5.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P87 Pin Register PCR8 Bit Name PCR87 Setting Value 0 1 Pin Function P87 input pin P87 output pin • P86 Pin Register PCR8 Bit Name PCR86 Setting Value 0 1 Pin Function P86 input pin P86 output pin • P85 Pin Register PCR8 Bit Name PCR85 Setting Value 0 1 Pin Function P85 input pin P85 output pin Rev. 6.00 Mar.
Section 9 I/O Ports • P84/FTIOD Pin Register TMRW TIOR1 Bit Name PWMD IOD2 IOD1 IOD0 PCR84 Pin Function 0 0 0 P84 input/FTIOD input pin 1 P84 output/FTIOD input pin Setting Value 0 1 0 PCR8 0 0 1 X FTIOD output pin 0 1 X X FTIOD output pin 1 X X X X X 0 P84 input/FTIOD input pin 1 P84 output/FTIOD input pin X PWM output pin [Legend] X: Don't care.
Section 9 I/O Ports • P82/FTIOB Pin Register TMRW TIOR0 Bit Name PWMB IOB2 IOB1 IOB0 PCR82 Pin Function 0 0 0 P82 input/FTIOB input pin 1 P82 output/FTIOB input pin Setting Value 0 1 0 PCR8 0 0 1 X FTIOB output pin 0 1 X X FTIOB output pin 1 X X X X X 0 P82 input/FTIOB input pin 1 P82 output/FTIOB input pin X PWM output pin [Legend] X: Don't care.
Section 9 I/O Ports 9.6 Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.6. PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 Port B PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.6 Port B Pin Configuration Port B has the following register. • Port data register B (PDRB) 9.6.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B.
Section 10 Timer A Section 10 Timer A Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10.1 shows a block diagram of timer A. 10.1 Features • Timer A can be used as an interval timer or a clock time base. • An interrupt is requested when the counter overflows. • Any of eight clock signals can be output from pin TMOW: 32.
Section 10 Timer A 1/4 PSW φW/4 φW/32 φW/16 φW/8 φW/4 TMA Internal data bus φW φW/128 φ ÷256* ÷64* φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32, φ/8 ÷8* φW/32 φW/16 φW/8 φW/4 ÷128* TCA TMOW PSS IRRTA [Legend] TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS: Prescaler S Note: * Can be selected only when the prescaler W output (øW/128) is used as the TCA input clock. Figure 10.1 Block Diagram of Timer A 10.
Section 10 Timer A 10.3 Register Descriptions Timer A has the following registers. • Timer mode register A (TMA) • Timer counter A (TCA) 10.3.1 Timer Mode Register A (TMA) TMA selects the operating mode, the divided clock output, and the input clock. Bit Bit Name Initial Value R/W Description 7 TMA7 0 R/W Clock Output Select 7 to 5 6 TMA6 0 R/W These bits select the clock output at the TMOW pin.
Section 10 Timer A Bit Bit Name Initial Value R/W Description 2 TMA2 0 R/W Internal Clock Select 2 to 0 1 TMA1 0 R/W 0 TMA0 0 R/W These bits select the clock input to TCA when TMA3 = 0. 000: φ/8192 001: φ/4096 010: φ/2048 011: φ/512 100: φ/256 101: φ/128 110: φ/32 111: φ/8 These bits select the overflow period when TMA3 = 1 (when a 32.768 kHz crystal oscillator with is used as φW). 000: 1s 001: 0.5 s 010: 0.25 s 011: 0.03125 s 1XX: Both PSW and TCA are reset [Legend] X: Don't care. 10.
Section 10 Timer A 10.4 Operation 10.4.1 Interval Timer Operation When bit TMA3 in TMA is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting of timer A resume immediately as an interval timer. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected.
Section 10 Timer A 10.5 Usage Note When the clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/φ (s) in the count cycle. Rev. 6.00 Mar.
Section 11 Timer V Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 11.1 shows a block diagram of timer V. 11.
Section 11 Timer V TCRV1 TCORB Trigger control TRGV Comparator TCNTV Internal data bus Clock select TMCIV Comparator φ PSS TCORA TMRIV Clear control TCRV0 Interrupt request control TMOV Output control TCSRV [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCRV1: Timer control register V1 PSS: Prescaler S CMIA: Compare-match interrupt A CMIB: Compare-match interrupt B OVI: O
Section 11 Timer V 11.2 Input/Output Pins Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV Trigger input TRGV Input Trigger input to initiate counting 11.3 Register Descriptions Time V has the following registers.
Section 11 Timer V 11.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle.
Section 11 Timer V Bit Bit Name Initial Value R/W Description 4 CCLR1 0 R/W Counter Clear 1 and 0 3 CCLR0 0 R/W These bits specify the clearing conditions of TCNTV. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared on the rising edge of the TMRIV pin. The operation of TCNTV after clearing depends on TRGE in TCRV1.
Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match.
Section 11 Timer V Bit Bit Name Initial Value R/W Description 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits select an output method for the TMOV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match.
Section 11 Timer V Bit Bit Name Initial Value R/W Description 1 1 Reserved This bit is always read as 1. 0 ICKS0 0 R/W Internal Clock Select 0 This bit selects clock signals to input to TCNTV in combination with CKS2 to CKS0 in TCRV0. Refer to table 11.2. 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals.
Section 11 Timer V φ Internal clock TCNTV input clock TCNTV N–1 N N+1 Figure 11.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock TCNTV N–1 N N+1 Figure 11.3 Increment Timing with External Clock φ TCNTV H'FF H'00 Overflow signal OVF Figure 11.4 OVF Set Timing Rev. 6.00 Mar.
Section 11 Timer V φ TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin Figure 11.6 TMOV Output Timing φ Compare match A signal TCNTV N H'00 Figure 11.7 Clear Timing by Compare Match Rev. 6.00 Mar.
Section 11 Timer V φ TMRIV(External counter reset input pin ) TCNTV reset signal N–1 TCNTV N H'00 Figure 11.8 Clear Timing by TMRIV Input 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2.
Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3.
Section 11 Timer V 11.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. 2. 3. 4. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence.
Section 11 Timer V TCORA write cycle by CPU T1 T2 T3 φ TCORA address Address Internal write signal TCNTV N N+1 TCORA N M TCORA write data Compare match signal Inhibited Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 11.13 Internal Clock Switching and TCNTV Operation Rev. 6.00 Mar.
Section 12 Timer W Section 12 Timer W The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems. 12.
Section 12 Timer W Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer W. Table 12.
Section 12 Timer W Internal clock: φ φ/2 φ/4 φ/8 External clock: FTCI FTIOA Clock selector FTIOB FTIOC Control logic FTIOD Comparator TIOR TSRW TIERW TCRW TMRW GRD GRC GRB Bus interface [Legend] TMRW: TCRW: TIERW: TSRW: TIOR: TCNT: GRA: GRB: GRC: GRD: IRRTW: GRA TCNT IRRTW Internal data bus Timer mode register W (8 bits) Timer control register W (8 bits) Timer interrupt enable register W (8 bits) Timer status register W (8 bits) Timer I/O control register (8 bits) Timer counter (16 bits
Section 12 Timer W 12.2 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.
Section 12 Timer W 12.3.1 Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Bit Bit Name Initial Value R/W Description 7 CTS 0 R/W Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 1 Reserved This bit is always read as 1. 5 BUFEB 0 R/W Buffer Operation B Selects the GRD function.
Section 12 Timer W 12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Bit Bit Name Initial Value R/W Description 7 CCLR 0 R/W Counter Clear The TCNT value is cleared by compare match A when this bit is 1. When it is 0, TCNT operates as a freerunning counter. 6 CKS2 0 R/W Clock Select 2 to 0 5 CKS1 0 R/W Select the TCNT clock source.
Section 12 Timer W Bit Bit Name Initial Value R/W Description 0 TOA 0 R/W Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1* [Legend] X: Don't care. Note: * The change of the setting is immediately reflected in the output value. 12.3.3 Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request.
Section 12 Timer W 12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Bit Bit Name Initial Value R/W Description 7 OVF 0 R/W Timer Overflow Flag [Setting condition] When TCNT overflows from H'FFFF to H'0000 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 6 1 Reserved 5 1 These bits are always read as 1.
Section 12 Timer W Bit Bit Name Initial Value R/W Description 1 IMFB 0 R/W Input Capture/Compare Match Flag B [Setting conditions] • TCNT = GRB when GRB functions as an output compare register • The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register [Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB 0 IMFA 0 R/W Input Capture/Compare Match Flag A [Setting conditions] • TCNT = GRA when GRA functions as an output compa
Section 12 Timer W Bit Bit Name Initial Value R/W Description 5 4 IOB1 IOB0 0 0 R/W R/W 3 1 2 IOA2 0 R/W 1 0 IOA1 IOA0 0 0 R/W R/W I/O Control B1 and B0 When IOB2 = 0, 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1, 00: Input capture at rising edge at the FTIOB pin 01: Input capture at falling edge at the FTIOB pin 1X: Input ca
Section 12 Timer W 12.3.6 Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit Bit Name Initial Value R/W Description 7 1 Reserved 6 IOD2 0 R/W This bit is always read as 1. I/O Control D2 Selects the GRD function.
Section 12 Timer W Bit Bit Name Initial Value R/W Description 1 IOC1 0 R/W I/O Control C1 and C0 0 IOC0 0 R/W When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1, 00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1X: Input capture to GRC at rising and falling edges
Section 12 Timer W 12.3.8 General Registers A to D (GRA to GRD) Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TIOR0 and TIOR1. When a general register is used as an input-compare register, its value is constantly compared with the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1.
Section 12 Timer W 12.4 Operation The timer W has the following operating modes. • Normal Operation • PWM Operation 12.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE in TIERW is set to 1, an interrupt request is generated. Figure 12.
Section 12 Timer W TCNT value GRA H'0000 Time CTS bit Flag cleared by software IMFA Figure 12.3 Periodic Counter Operation By setting a general register as an output compare register, compare match A, B, C, or D can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure 12.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output is selected for compare match A, and 0 output is selected for compare match B.
Section 12 Timer W Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B. TCNT value H'FFFF GRA GRB Time H'0000 FTIOA Toggle output FTIOB Toggle output Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B.
Section 12 Timer W The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured. Figure 12.7 shows an example of input capture when both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates as a free-running counter.
Section 12 Timer W Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation, the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
Section 12 Timer W Figure 12.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 1: initial output values are set to 1). TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.9 PWM Mode Example (1) Figure 12.10 shows another example of operation in PWM mode.
Section 12 Timer W Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs.
Section 12 Timer W Figures 12.12 and 12.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%. TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 0% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 100% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously.
Section 12 Timer W TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 100% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 0% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 0% FTIOB Duty 100% Figure 12.
Section 12 Timer W 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure 12.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted correctly. φ Internal clock Rising edge TCNT input clock TCNT N N+1 N+2 Figure 12.
Section 12 Timer W 12.5.2 Output Compare Output Timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next counter clock pulse is input. Figure 12.16 shows the output compare timing.
Section 12 Timer W 12.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. φ Input capture input Input capture signal N–1 TCNT N N+1 N+2 N GRA to GRD Figure 12.17 Input Capture Input Signal Timing 12.5.
Section 12 Timer W 12.5.5 Buffer Operation Timing Figures 12.19 and 12.20 show the buffer operation timing. φ Compare match signal TCNT N GRC, GRD M N+1 M GRA, GRB Figure 12.19 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N GRA, GRB M GRC, GRD N+1 N N+1 M N Figure 12.20 Buffer Operation Timing (Input Capture) Rev. 6.00 Mar.
Section 12 Timer W 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count).
Section 12 Timer W 12.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 12.22 shows the timing of the IMFA to IMFD flag setting at input capture. φ Input capture signal TCNT N N GRA to GRD IMFA to IMFD IRRTW Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture 12.5.
Section 12 Timer W 12.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T2 state of a TCNT write cycle.
Section 12 Timer W Previous clock New clock Count clock TCNT N+1 N N+2 N+3 The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 12.25 Internal Clock Switching and TCNT Operation 5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs.
Section 12 Timer W TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is the 1 output state, and is set to the toggle output or the 0 output on compare match B. When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the FTIOB signal low; the FTIOB signal remains high.
Section 12 Timer W Rev. 6.00 Mar.
Section 13 Watchdog Timer Section 13 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 13.1.
Section 13 Watchdog Timer 13.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value. Bit Bit Name Initial Value R/W Description 7 B6WI 1 R/W Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0.
Section 13 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 WDON 0 R/W Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0.
Section 13 Watchdog Timer 13.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1. 3 CKS3 1 R/W Clock Select 3 to 0 2 CKS2 1 R/W Select the clock to be input to TCWD.
Section 13 Watchdog Timer 13.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 256 φosc clock cycles.
Section 13 Watchdog Timer Rev. 6.00 Mar.
Section 14 Serial Communication Interface 3 (SCI3) Section 14 Serial Communication Interface 3 (SCI3) Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
Section 14 Serial Communication Interface 3 (SCI3) SCK3 External clock Internal clock (φ/64, φ/16, φ/4, φ) Baud rate generator BRR BRC Clock Transmit/receive control circuit Internal data bus SMR SCR3 SSR TXD TSR TDR RXD RSR RDR Interrupt request (TEI, TXI, RXI, ERI) [Legend] Receive shift register RSR: Receive data register RDR: Transmit shift register TSR: Transmit data register TDR: Serial mode register SMR: SCR3: Serial control register 3 Serial status register SSR: Bit rate register BRR
Section 14 Serial Communication Interface 3 (SCI3) 14.3 Register Descriptions The SCI3 has the following registers. • • • • • • • • Receive shift register (RSR) Receive data register (RDR) Transmit shift register (TSR) Transmit data register (TDR) Serial mode register (SMR) Serial control register 3 (SCR3) Serial status register (SSR) Bit rate register (BRR) 14.3.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/W Transmit Data Register Empty Displays whether TDR contains transmit data.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 PER 0 R/W Parity Error [Setting condition] When a parity error is generated during reception [Clearing condition] When 0 is written to PER after reading PER = 1 2 TEND 1 R Transmit End [Setting conditions] • When the TE bit in SCR3 is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing conditions] 1 MPBR 0 R • When 0 is written to TEND after r
Section 14 Serial Communication Interface 3 (SCI3) 14.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 14.3 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 14.2 and 14.3 are values in active (highspeed) mode. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 2 2.097152 2.4576 Bit Rate (bits/s) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 –0.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728 Error (%) 8 Bit Rate (bit/s) n N Error (%) n 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ (MHz) 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 181 0.16 2 191 0.00 2 207 0.16 300 2 90 0.16 2 95 0.00 2 103 0.16 600 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 181 0.16 0 191 0.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) 2 n N 4 n N 8 n N 10 n N 16 n N 110 3 70 — — — — — — 250 2 124 2 249 3 124 — — 3 249 500 1 249 2 124 2 249 — — 3 124 1k 1 124 1 249 2 124 — — 2 249 2.
Section 14 Serial Communication Interface 3 (SCI3) 14.4 Operation in Asynchronous Mode Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.2 SCI3 Initialization Follow the flowchart as shown in figure 14.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. [1] Set the clock selection in SCR3.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.3 Data Transmission Figure 14.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] Read TDRE flag in SSR TDRE = 1 No Yes Write transmit data to TDR [2] All data transmitted? Yes No [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.4 Serial Data Reception Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit. 2.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.8 shows a sample flowchart for serial data reception. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR No [2] RDRF = 1 Yes Read receive data in RDR Yes (A) All data received? [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR.
Section 14 Serial Communication Interface 3 (SCI3) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Break? Yes No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 14.8 Sample Serial Reception Data Flowchart (2) Rev. 6.00 Mar.
Section 14 Serial Communication Interface 3 (SCI3) 14.5 Operation in Clocked Synchronous Mode Figure 14.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.3 Serial Data Transmission Figure 14.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] Read TDRE flag in SSR TDRE = 1 No Yes Write transmit data to TDR [2] All data transmitted? [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. 2. 3. 4. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. The SCI3 stores the received data in RSR.
Section 14 Serial Communication Interface 3 (SCI3) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.13 shows a sample flowchart for serial data reception.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.5 Simultaneous Serial Data Transmission and Reception Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Section 14 Serial Communication Interface 3 (SCI3) 14.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 14 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle = receiving station specification (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 14.
Section 14 Serial Communication Interface 3 (SCI3) 14.6.1 Multiprocessor Serial Data Transmission Figure 14.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
Section 14 Serial Communication Interface 3 (SCI3) 14.6.2 Multiprocessor Serial Data Reception Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure 14.
Section 14 Serial Communication Interface 3 (SCI3) [5] No Error processing OER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Yes [A] Framing error processing Clear OER, and FER flags in SSR to 0 Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 6.00 Mar.
Section 14 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame 1 frame MPIE RDRF RDR value ID1 LSI operation User processing RXI interrupt request is not generated, and RDR retains its state RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again (a)
Section 14 Serial Communication Interface 3 (SCI3) 14.7 Interrupts The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6 shows the interrupt sources. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) 14.8.2 Mark State and Break Sending When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1.
Section 14 Serial Communication Interface 3 (SCI3) Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design.
2 Section 15 I C Bus Interface (IIC) Section 15 I2C Bus Interface (IIC) The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. 15.
2 Section 15 I C Bus Interface (IIC) Figure 15.1 shows a block diagram of the I2C bus interface. Figure 15.2 shows an example of I/O pin connections to external circuits. The I/O pins are NMOS open drains. Set the upper limit of voltage applied to the power supply (VCC) voltage range + 0.3 V, i.e. 5.8 V.
2 Section 15 I C Bus Interface (IIC) VDD VCC SCL SCL SDA SDA SCL in SDA in SCL SDA SDA out (Master) SCL in This LSI SCL out SCL out SDA in SDA in SDA out SDA out SCL in (Slave 1) SCL SDA SCL out (Slave 2) Figure 15.2 I2C Bus Interface Connections (Example: This LSI as Master) 15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I2C bus interface. Table 15.
2 Section 15 I C Bus Interface (IIC) 15.3 Register Descriptions The I2C bus interface has the following registers. ICDR, SARX, ICMR, and SAR are allocated to one address, and registers that can be accessed depend on the ICE bit in ICCR. When ICE = 0. SAR and SARX can be accessed. When ICE = 1, ICMR and ICDR can be accessed.
2 Section 15 I C Bus Interface (IIC) The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the TDRE and RDRF flags affects the status of the interrupt flags.
2 Section 15 I C Bus Interface (IIC) 15.3.2 Slave Address Register (SAR) SAR selects the slave address and selects the communication format. SAR can be written and read only when the ICE bit is cleared to 0 in ICCR. Bit Bit Name Initial Value R/W Description 7 SVA6 0 R/W Slave Address 6 to 0 6 SVA5 0 R/W Sets a slave address 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W 15.3.
2 Section 15 I C Bus Interface (IIC) Table 15.2 Communication Format SAR SARX FS FSX I2C Transfer Format 0 0 SAR and SARX are used as the slave addresses with the I2C bus format. 0 1 Only SAR is used as the slave address with the I2C bus format. 1 0 Only SARX is used as the slave address with the I2C bus format. 1 1 Clock synchronous serial format (SAR and SARX are invalid) 15.3.4 I2C Bus Mode Register (ICMR) The I2C bus mode register (ICMR) sets the transfer format and transfer rate.
2 Section 15 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. With the I2C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low.
2 Section 15 I C Bus Interface (IIC) Table 15.3 I2C Transfer Rate TSCR ICMR Bit 0 Bit 5 Bit 4 Bit 3 Transfer Rate IICX CKS2 CKS1 CKS0 Clock φ = 5 MHz φ = 8 MHz φ = 10 MHz φ = 16 MHz 0 0 0 0 φ/28 179MHz 286kHz 357kHz 571kHz 0 0 0 1 φ/40 125kHz 200kHz 250kHz 400kHz 0 0 1 0 φ/48 104kHz 167kHz 208kHz 333kHz 0 0 1 1 φ/64 78.1kHz 125kHz 156kHz 250kHz 0 1 0 0 φ/80 62.5kHz 100kHz 125kHz 200kHz 0 1 0 1 φ/100 50.0kHz 80.
2 Section 15 I C Bus Interface (IIC) 15.3.5 I2C Bus Control Register (ICCR) I2C bus control register (ICCR) consists of the control bits and interrupt request flags of I2C bus interface. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I2C Bus Interface Enable 2 When this bit is set to 1, the I C bus interface module is enabled to send/receive data and drive the bus since it is connected to the SCL and SDA pins. ICMR and ICDR can be accessed.
2 Section 15 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 3 ACKE 0 R/W Acknowledge Bit Judgement Selection 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. 1: If the acknowledge bit is 1, continuous transfer is interrupted.
2 Section 15 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 1 IRIC 0 R/W I2C Bus Interface Interrupt Request Flag Also see table 15.4.
2 Section 15 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 0 SCP 1 W Start Condition/Stop Condition Prohibit The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. 15.3.
2 Section 15 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 5 IRTR 0 R/W I2C Bus Interface Continuous Transmission/Reception Interrupt Request Flag [Setting conditions] In I2C bus interface slave mode • When the TDRE or RDRF flag is set to 1 when AASX = 1 2 In I C bus interface other modes • When the TDRE or RDRF flag is set to 1 [Clearing conditions] 4 AASX 0 R/W • When 0 is written in IRTR after reading IRTR = 1 • When the IRIC flag is cleared to 0 Second Slave
2 Section 15 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 2 AAS 0 R/W Slave Address Recognition Flag [Setting condition] When the slave address or general call address is detected in slave receive mode and FS = 0.
2 Section 15 I C Bus Interface (IIC) 15.3.7 Timer Serial Control Register (TSCR) The timer serial control register (TSCR) is an 8-bit readable/writable register that controls the operating modes. Bit Bit Name Initial Value R/W Description 7 to 2 − All 1 − Reserved 1 IICRST 0 R/W I2C Control Unit Reset This bit is always read as 1 and cannot be modified. 2 Resets the control unit except for the I C registers.
2 Section 15 I C Bus Interface (IIC) Table 15.
2 Section 15 I C Bus Interface (IIC) (a) I2C bus format (FS = 0 or FSX = 0) S SLA R/W A DATA A A/A P 1 7 1 1 n 1 1 1 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m ≥ 1) m (b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0) S SLA R/W A DATA A/A S SLA R/W A DATA A/A P 1 7 1 1 n1 1 1 7 1 1 n2 1 1 1 m1 1 m2 n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 ≥ 1) Figure 15.
2 Section 15 I C Bus Interface (IIC) 15.4.2 Master Transmit Operation When data is set to ICDR during the period between the execution of an instruction to issue a start condition and the creation of the start condition, the data may not be output normally, because there will be a contention between a generation of a start condition and an output of data.
2 Section 15 I C Bus Interface (IIC) 9. Write the transmit data to ICDR. As indicating the end of the transfer, and so the IRIC flag is cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in the step [6]. Transmission of the next frame is performed in synchronization with the internal clock. 10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse.
2 Section 15 I C Bus Interface (IIC) 15.4.3 Master Receive Operation The data buffer of the I2C module can receive data consecutively since it consists of ICDRR and ICDRS. However, if the completion of receiving the last data is delayed, there will be a contention between the instruction to issue a stop condition and the SCl clock output to receive the next data, and may generate unnecessary clocks or fix the output level of the SDA line as low.
2 Section 15 I C Bus Interface (IIC) 9. Clear the IRIC flag in ICCR to cancel wait operation. The master device outputs the 9th clock and drives SDA at the 9th receive clock pulse to return an ackowledge signal. Data can be received continuously by repeating the step [5] to [9]. 10. Set the ACKB bit in ICSR to 1 so as to return “No acknowledge” data. Also set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. 11. Clear IRIC flag to 0 to release from the Wait State. 12.
2 Section 15 I C Bus Interface (IIC) SCL (master output) 8 9 Bit 0 SDA (slave output) Data 2 SDA (master output) [8] 1 2 Bit 7 Bit 6 [5] 3 Bit 5 4 5 6 7 8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 3 9 1 Bit 7 [8] A [5] 2 Bit 6 Data 4 A IRIC IRTR ICDR Data 1 Data 3 Data 2 [6] ICDR read (Data 3) User processing [9] IRIC clearance [6] ICDR read (Data 2) [7] IRIC clearance [9] IRIC clearance [7] IRIC clearance Figure 15.
2 Section 15 I C Bus Interface (IIC) 5. Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0.
2 Section 15 I C Bus Interface (IIC) SCL (master output) 7 8 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (slave output) SDA (master output) Data 1 [4] [4] Data 2 SDA (slave output) A RDRF IRIC Interrupt request generation ICDRS Data 1 ICDRR Data 1 User processing Interrupt request generation Data 2 Data 2 [5] ICDR read [5] IRIC clearance Figure 15.8 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) Rev. 6.
2 Section 15 I C Bus Interface (IIC) 15.4.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. 2.
2 Section 15 I C Bus Interface (IIC) Slave receive mode SCL (master output) 8 Slave transmit mode 9 1 2 A Bit 7 Bit 6 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 SCL (slave output) SDA (slave output) Data 1 [2] SDA (master output) R/W Data 2 A TDRE [3] Interrupt request generation IRIC Interrupt request generation ICDRT Interrupt request generation Data 1 ICDRS Data 2 Data 1 User processing [3] IRIC clearance [3] ICDR write Data 2 [3] ICDR
2 Section 15 I C Bus Interface (IIC) 15.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 15.11 shows the IRIC set timing and SCL control.
2 Section 15 I C Bus Interface (IIC) 15.4.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 15.12 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
2 Section 15 I C Bus Interface (IIC) 15.4.9 Sample Flowcharts Figures 15.13 to 15.16 show sample flowcharts for using the I2C bus interface in each mode. Start Initialize [1] Initialization Read BBSY in ICCR No [2] Test the status of the SCL and SDA lines. BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR [3] Select master transmit mode.
2 Section 15 I C Bus Interface (IIC) Master receive operation Set TRS = 0 in ICCR [1] Select receive mode. Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR Read ICDR [2] Start receiving. The first read is a dummy read. After reading ICDR, please clear IRIC immediately. Clear IRIC in ICCR Read IRIC in ICCR No [3] Wait for 1 byte to be received. IRIC = 1? Yes Yes Last receive? No [4] Clear IRIC. (to end the wait insertion) Clear IRIC in ICCR Read IRIC in ICCR No [5] Wait for 1 byte to be received.
2 Section 15 I C Bus Interface (IIC) Start Initialize Set MST = 0 and TRS = 0 in ICCR [1] Set ACKB = 0 in ICSR Read IRIC in ICCR No [2] IRIC = 1? Yes Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? No General call address processing * Description omitted Yes Read TRS in ICCR No TRS = 0? Slave transmit mode Yes Last receive? Yes No Read ICDR [3] [1] Select slave receive mode. Clear IRIC in ICCR [2] Wait for the first byte to be received (slave address). Read IRIC in ICCR [3] Start receiving.
2 Section 15 I C Bus Interface (IIC) Slave transmit mode [1] Set transmit data for the second and subsequent bytes. Clear IRIC in ICCR Write transmit data in ICDR [1] [2] Wait for 1 byte to be transmitted. [3] Test for end of transfer. Clear IRIC in ICCR [4] Set slave receive mode. [5] Dummy read (to release the SCL line).
2 Section 15 I C Bus Interface (IIC) 15.5 Usage Notes 1. In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition.
2 Section 15 I C Bus Interface (IIC) 5. The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended.
2 Section 15 I C Bus Interface (IIC) Table 15.7 I2C Bus Timing (with Maximum Influence of tsr/tsf) Time Indication (at Maximum Transfer Rate) [ns] 2 Item tcyc Indication tSCLHO 0.5tSCLO (–tSr) tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO (master) 0.5tSCLO (–tSf ) 0.5tSCLO –1tcyc ( –tSr ) tsr/tsf Influence (Max.) I C Bus Specification φ = 5 MHz (Min.
2 Section 15 I C Bus Interface (IIC) 7. Note on ICDR Read at end of Master Reception To halt reception after completion of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes the SDA pin from low to high when the SCL pin is high, and generates the stop condition.
2 Section 15 I C Bus Interface (IIC) [1] Wait for end of 1-byte transfer No IRIC = 1? [1] [2] Determine whether SCL is low Yes Clear IRIC in ICSR [3] Issue restart condition instruction for transmission No Start condition issuance? Other processing [4] Determine whether start condition is generated or not Yes [5] Set transmit data (slave address + R/W) Read SCL pin No SCL = Low? [2] Yes Write BBSY = 1, SCP = 0 (ICSR) [3] No IRIC = 1? [4] Note: Program so that processing from [3] to [5] is
2 Section 15 I C Bus Interface (IIC) • Notes on WAIT Function Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the WAIT function due to the failure of the WAIT insertion after the 8th clock fall.
2 Section 15 I C Bus Interface (IIC) • Notes on TRS Bit Setting and ICDR Register Access Conditions to cause this failure Low-fixation of the SCL pins is cancelled incorrectly when the following conditions are satisfied. Master mode: Figure 15.19 shows the notes on ICDR reading (TRS = 1) in master mode. (a) When previously received 2-byte data remains in ICDR unread (ICDRS are full). (b) Reads ICDR register after switching to transmit mode (TRS = 1).
2 Section 15 I C Bus Interface (IIC) Along with ICDRT → ICDRR transfer Cancel condition of SCL = Low fixation is set. Stop condition Start condition A SDA SCL 8 Address 9 1 2 3 4 5 A 6 7 8 9 Data 1 2 3 4 (b) TRS = 1 TRS bit TDRE bit (a) TDRE = 0 TRS = 0 setting ICDR write Automatic TRS = 1 setting by receiving R/W = 1 Figure 15.
2 Section 15 I C Bus Interface (IIC) Rev. 6.00 Mar.
Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1. 16.1 • • • • • • • • Features 10-bit resolution Eight input channels (four channels for the 42-pin version) Conversion time: at least 4.
Section 16 A/D Converter Module data bus *AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer 10-bit D/A Bus interface Successive approximations register AVCC Internal data bus A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + φ/4 Control circuit Comparator Sample-andhold circuit ADTRG [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Note: AN4, AN5, AN
Section 16 A/D Converter 16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. The eight analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the analog block in the A/D converter. Table 16.
Section 16 A/D Converter 16.3 Register Description The A/D converter has the following registers. • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion.
Section 16 A/D Converter 16.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Section 16 A/D Converter Bit Bit Name Initial Value R/W Description 2 CH2 0 R/W Channel Select 0 to 2 1 CH1 0 R/W Select analog input channels. 0 CH0 0 R/W When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 to AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4 100: AN4 101: AN5 101: AN4 to AN5 110: AN6 110: AN4 to AN6 111: AN7 111: AN4 to AN7 AN4, AN5, AN6, and AN7 do not exist in the 42-pin version. 16.3.
Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 16.4.
Section 16 A/D Converter 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows the A/D conversion time. As indicated in figure 16.2, the A/D conversion time includes tD and the input sampling time.
Section 16 A/D Converter Table 16.3 A/D Conversion Time (Single Mode) CKS = 0 Item Symbol Min CKS = 1 Typ Max Min Typ Max A/D conversion start delay tD 6 — 9 4 — 5 Input sampling time tSPL — 31 — — 15 — A/D conversion time tCONV 131 — 134 69 — 70 Note: All values represent the number of states. 16.4.4 External Trigger Input Timing The A/D conversion can also be started by an external trigger input.
Section 16 A/D Converter 16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 16.5).
Section 16 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 16.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 16.5 A/D Conversion Accuracy Definitions (2) Rev. 6.00 Mar.
Section 16 A/D Converter 16.6 Usage Notes 16.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 17 EEPROM Section 17 EEPROM This LSI has an on-chip 512-byte EEPROM. The block diagram of the EEPROM is shown in figure 17.1. 17.1 Features • Two writing methods: 1-byte write Page write: Page size 8 bytes • Three reading methods: Current address read Random address read Sequential read • Acknowledge polling possible • Write cycle time: 10 ms (power supply voltage Vcc = 2.
Section 17 EEPROM EEPROM Data bus Y decoder H'FF10 SDA SCL I2C bus interface control circuit Y-select/ Sense amp. Memory array User area (512 bytes) X decoder Key control circuit Address bus EEPROM Key register (EKR) Slave address register ESAR Power-on reset Booster circuit EEPROM module [Legend] ESAR: Register for referring the slave address (specifies the slave address of the memory array) Figure 17.1 Block Diagram of EEPROM Rev. 6.00 Mar.
Section 17 EEPROM 17.2 Input/Output Pins Pins used in the EEPROM are listed in table 17.1. Table 17.1 Pin Configuration Pin name Symbol Input/ Output Serial clock pin SCL Input The SCL pin is used to control serial input/output data timing. The data is input at the rising edge of the clock and output at the falling edge of the clock. The SCL pin needs to be pulled up by resistor as that pin is open-drain driven structure of the 2 I C pin.
Section 17 EEPROM 17.4 Operation 17.4.1 EEPROM Interface This LSI has a multi-chip structure with two internal chips of F-ZTAT™ HD64F3664 and 512byte EEPROM. The EEPROM interface is the I2C bus interface. This I2C bus is open to the outside, so the communication with the external devices connected to the I2C bus can be made. 17.4.2 Bus Format and Timing The I2C bus format and the I2C bus timing follow section 15.4.1, I2C Bus Data Format. The bus formats specific for the EEPROM are the following two.
Section 17 EEPROM 17.4.3 Start Condition A high-to-low transition of the SDA input with the SCL input high is needed to generate the start condition for starting read, write operation. 17.4.4 Stop Condition A low-to-high transition of the SDA input with the SCL input high is needed to generate the stop condition for stopping read, write operation. The standby operation starts after a read sequence by a stop condition.
Section 17 EEPROM 17.4.6 Slave Addressing The EEPROM device receives a 7-bit slave address and a 1-bit R/W code following the generation of the start conditions. The EEPROM enables the chip for a read or a write operation with this operation. The slave address consists of a former 4-bit device code and latter 3-bit slave address as shown in table 17.2. The device code is used to distinguish device type and this LSI uses "1010" fixed code in the same manner as in a general-purpose EEPROM.
Section 17 EEPROM 17.4.7 Write Operations There are two types write operations; byte write operation and page write operation. To initiate the write operation, input 0 to R/W code following the slave address. 1. Byte Write A write operation requires an 8-bit data of a 7-bit slave address with R/W code = "0". Then the EEPROM sends acknowledgement "0" at the ninth bit. This enters the write mode. Then, two bytes of the memory address are received from the MSB side in the order of upper and lower.
Section 17 EEPROM Addresses in the page are incremented at each receipt of the write data and the write data can be input up to 8 bytes. If the LSB 3 bits (A2 to A0) in the EEPROM address reach the last address of the page, the address will roll over to the first address of the same page. When the address is rolled over, write data is received twice or more to the same address, however, the last received data is valid.
Section 17 EEPROM 17.4.9 Read Operation There are three read operations; current address read, random address read, and sequential read. Read operations are initiated in the same way as write operations with the exception of R/W = 1. 1. Current Address Read The internal address counter maintains the (n+1) address that is made by the last address (n) accessed during the last read or write operation, with incremented by one.
Section 17 EEPROM 2. Random Address Read This is a read operation with defined read address. A random address read requires a dummy write to set read address. The EEPROM receives a start condition, slave address + R/W code (R/W = 0), memory address (upper) and memory address (lower) sequentially. The EEPROM outputs acknowledgement "0" after receiving memory address (lower) then enters a current address read with receiving a start condition again.
Section 17 EEPROM SCL 1 2 3 4 5 6 7 8 9 SDA Slave address R/W ACK 1 8 9 D7 D0 Read Data ACK · · · · 1 8 D7 D0 Read Data 9 ACK Start condition Stop conditon [Legend] R/W: R/W code (0 is for a write and 1 is for a read) ACK: acknowledge Figure 17.7 Sequential Read Operation (when current address read is used) 17.5 Usage Notes 17.5.1 Data Protection at VCC On/Off When VCC is turned on or off, the data might be destroyed by malfunction.
Section 17 EEPROM 17.5.3 Noise Suppression Time This EEPROM has a noise suppression function at SCL and SDA inputs, that cuts noise of width less than 50 ns. Be careful not to allow noise of width more than 50 ns because the noise of with more than 50 ms is recognized as an active pulse. Rev. 6.00 Mar.
Section 18 Power Supply Circuit Section 18 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V.
Section 18 Power Supply Circuit 18.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 18.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
Section 19 List of Registers Section 19 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. • • • • Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated. 2.
Section 19 List of Registers 19.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Address Module Name Data Bus Width Access State 8 H'FF80 Timer W 8 2 8 H'FF81 Timer W 8 2 8 H'FF82 Timer W 8 2 Abbreviation Bit No.
Section 19 List of Registers Module Name Data Bus Width Access State Register Name Abbreviation Transmit data register TDR 8 H'FFAB SCI3 8 3 Serial status register SSR 8 H'FFAC SCI3 8 3 Bit No.
Section 19 List of Registers Address Module Name Data Bus Width Access State 8 H'FFDD I/O port 8 2 PMR1 8 H'FFE0 I/O port 8 2 Port mode register 5 PMR5 8 H'FFE1 I/O port 8 2 Port control register 1 PCR1 8 H'FFE4 I/O port 8 2 Port control register 2 PCR2 8 H'FFE5 I/O port 8 2 Register Name Abbreviation Bit No.
Section 19 List of Registers 19.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines.
Section 19 List of Registers Register Name Bit 7 SMR COM CHR PE PM STOP MP BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 Module Name CKS1 CKS0 SCI3 BRR1 BRR0 Bit 1 SCR3 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SSR TDRE RDRF OER FER PER TEND MPBR MPBT RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 ADDRA AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — ADDRB AD9 AD8
Section 19 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name PDR7 — P76 P75 P74 — — — — I/O port PDR8 P87 P86 P85 P84 P83 P82 P81 P80 PDRB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PMR1 IRQ3 IRQ2 IRQ1 IRQ0 — — TXD TMOW PMR5 — — WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 PCR1 PCR17 PCR16 PCR15 PCR14 — PCR12 PCR11 PCR10 PCR2 — — — — PCR22 PCR21 PCR20 — 2 2 PCR5 PCR57* PCR56* PCR55 PCR54 PCR53 PCR52 PCR51 PCR5
Section 19 List of Registers 19.
Section 19 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module ADDRA Initialized — — Initialized Initialized Initialized A/D converter ADDRB Initialized — — Initialized Initialized Initialized ADDRC Initialized — — Initialized Initialized Initialized ADDRD Initialized — — Initialized Initialized Initialized ADCSR Initialized — — Initialized Initialized Initialized ADCR Initialized — — Initialized Initialized Initialized TCS
Section 19 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module PCR1 Initialized — — — — — I/O port PCR2 Initialized — — — — — PCR5 Initialized — — — — — PCR7 Initialized — — — — — PCR8 Initialized — — — — — SYSCR1 Initialized — — — — — Power-down SYSCR2 Initialized — — — — — Power-down IEGR1 Initialized — — — — — Interrupts IEGR2 Initialized — — — — — Interrupts IENR1 Initialized — — — — — Int
Section 20 Electrical Characteristics Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20.1 Absolute Maximum Ratings Item Symbol Power supply voltage VCC Analog power supply voltage AVCC Ports other than Port B and VIN X1 –0.3 to VCC +0.3 V Port B –0.3 to AVCC +0.3 V Input voltage X1 Value Unit Note –0.3 to +7.0 V * –0.3 to +7.0 V –0.3 to 4.
Section 20 Electrical Characteristics Power Supply Voltage and Operating Frequency Range φ (MHz) φ SUB (kHz) 16.0 16.384 10.0 8.192 4.096 1.0 3.0 4.0 5.5 VCC (V) • AVCC = 3.3 V to 5.5 V • Active mode • Sleep mode (When MA2 = 0 in SYSCR2) φ (kHz) 2000 1250 78.125 3.0 4.0 5.5 VCC (V) • AVCC = 3.3 V to 5.5 V • Active mode • Sleep mode (When MA2 = 1 in SYSCR2) Rev. 6.00 Mar. 24, 2006 Page 312 of 412 REJ09B0142-0600 3.0 4.0 5.5 • AVCC = 3.3 V to 5.
Section 20 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range φ (MHz) 16.0 10.0 2.0 3.3 4.0 5.5 AVCC (V) • VCC = 3.0 V to 5.5 V • Active mode • Sleep mode Rev. 6.00 Mar.
Section 20 Electrical Characteristics 20.2.2 DC Characteristics Table 20.2 DC Characteristics (1) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C unless otherwise indicated. Values Item Symbol Applicable Pins Input high VIH voltage RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMRIV, Test Condition Min Typ Max Unit VCC = 4.0 V to 5.5 V VCC × 0.8 — VCC + 0.3 V VCC × 0.9 — VCC + 0.3 VCC × 0.7 — VCC + 0.3 VCC × 0.8 — VCC + 0.3 AVCC + 0.
Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Output high voltage VOH P10 to P12, P14 to P17, P20 to P22, P50 to P55, P74 to P76, P80 to P87, VCC = 4.0 V to 5.5 V VCC – 1.0 P56, P57* Min Typ Max Unit — — V VCC – 0.5 — — VCC = 4.0 V to 5.5 V VCC – 2.5 — — — — — 0.6 — — 0.4 VCC = 4.0 V to 5.5 V — — 1.5 — 1.0 — 0.4 — — 0.4 VCC = 4.0 V to 5.5 V — — 0.6 — 0.4 Notes –IOH = 1.5 mA –IOH = 0.1 mA V –IOH = 0.1 mA VCC = 3.
Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Input/ output leakage current | IIL | Min Typ Max Unit Notes OSC1, RES, NMI, VIN = 0.5 V to WKP0 to WKP5, (VCC – 0.5 V) IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, RXD, SCK3, SCL, SDA — — 1.0 µA P10 to P12, P14 to P17, P20 to P22, 1 P50 to P57* , P74 to P76, P80 to P87, VIN = 0.5 V to (VCC – 0.5 V) — — 1.0 µA PB0 to PB7 VIN = 0.5 V to (AVCC – 0.5 V) — — 1.
Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes Sleep mode supply current ISLEEP1 VCC Sleep mode 1 VCC = 5.0 V, fOSC = 16 MHz — 11.5 17.0 mA * Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz — 6.5 — Sleep mode 2 VCC = 5.0 V, fOSC = 16 MHz — 1.7 2.5 Sleep mode 2 VCC = 3.0 V, fOSC = 10 MHz — 1.1 — VCC = 3.0 V 32-kHz crystal resonator (φSUB = φW/2) — 35.0 70.0 VCC = 3.0 V 32-kHz crystal resonator (φSUB = φW/8) — 25.
Section 20 Electrical Characteristics Mode RES Pin Active mode 1 VCC Active mode 2 Sleep mode 1 Internal State Other Pins Oscillator Pins Operates VCC Main clock: ceramic or crystal resonator Operates (φosc/64) VCC Sleep mode 2 Only timers operate Subclock: Pin X1 = VSS VCC Only timers operate (φosc/64) Subactive mode VCC Operates VCC Subsleep mode VCC Only timers operate VCC Main clock: ceramic or crystal resonator Subclock: crystal resonator Standby mode VCC CPU and timers both
Section 20 Electrical Characteristics Table 20.2 DC Characteristics (3) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated. Applicable Values Item Symbol Pins Allowable output low current (per pin) IOL Output pins except VCC = 4.0 V to port 8, SCL, and 5.5 V SDA Port 8 Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) ∑IOL I –IOH I I –∑IOH I Test Condition Min Typ Max Unit — — 2.
Section 20 Electrical Characteristics 20.2.3 AC Characteristics Table 20.3 AC Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Item Symbol System clock oscillation frequency fOSC System clock (φ) cycle time tcyc Applicable Pins Test Condition OSC1, OSC2 Values Typ Max Unit Reference Figure VCC = 4.0 V to 5.5 V 2.0 — 16.0 MHz * 2.0 — 10.0 MHz 1 — 64 tOSC — — 12.8 µs Min Subclock oscillation fW frequency X1, X2 — 32.
Section 20 Electrical Characteristics Applicable Values Item Symbol Pins Test Condition RES pin low width tREL RES Min Reference Typ Max Unit Figure At power-on and in trc modes other than those below — — ms Figure 20.
Section 20 Electrical Characteristics Table 20.4 I2C Bus Interface Timing VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified.
Section 20 Electrical Characteristics Table 20.5 Serial Interface (SCI3) Timing VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Applicable Item Input clock cycle Asynchronous Symbol Pins tScyc SCK3 Values Test Condition Clocked synchronous Input clock pulse width tSCKW SCK3 Transmit data delay time (clocked synchronous) tTXD TXD Receive data setup time (clocked synchronous) tRXS Receive data hold time tRXH (clocked synchronous) RXD RXD VCC = 4.
Section 20 Electrical Characteristics 20.2.4 A/D Converter Characteristics Table 20.6 A/D Converter Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Item Symbol Applicable Test Pins Condition Values Reference Min Typ Max Unit Figure V * Analog power supply AVCC voltage AVCC 3.3 VCC 5.5 Analog input voltage AN0 to AN7 VSS – 0.3 — AVCC + 0.3 V — 2.0 mA AVIN Analog power supply AIOPE current AVCC AVCC = 5.
Section 20 Electrical Characteristics Item Symbol Applicable Test Pins Condition Conversion time (single mode) Values Min AVCC = 4.0 V 134 to 5.5 V Reference Typ Max Unit Figure — — tcyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2.
Section 20 Electrical Characteristics 20.2.6 Memory Characteristics Table 20.8 Flash Memory Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Section 20 Electrical Characteristics Test Item Erase Symbol Values Condition Min Typ Max Unit Wait time after SWE 1 bit setting* x 1 — — µs Wait time after ESU 1 bit setting* y 100 — — µs 1 6 Wait time after E bit setting* * 1 Wait time after E bit clear* 1 Wait time after ESU bit clear* z 10 — 100 ms α 10 — — µs β 10 — — µs Wait time after EV bit setting* γ 20 — — µs 1 ε 2 — — µs η 4 — — µs 100 — — µs — — 120 Times 1 Wait time after dummy w
Section 20 Electrical Characteristics 20.2.7 EEPROM Characteristics Table 20.9 EEPROM Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Section 20 Electrical Characteristics 20.3 Electrical Characteristics (Mask ROM Version) 20.3.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range φ OSC (MHz) φ W (kHz) 16.0 32.768 10.0 2.0 2.7 4.0 5.5 • AVCC = 3.0 V to 5.5 V • Active mode • Sleep mode VCC (V) 2.7 4.0 5.5 VCC (V) • AVCC = 3.0 V to 5.5 V • All operating modes Rev. 6.00 Mar.
Section 20 Electrical Characteristics Power Supply Voltage and Operating Frequency Range φ (MHz) φ SUB (kHz) 16.0 16.384 10.0 8.192 4.096 1.0 2.7 φ (kHz) 4.0 5.5 VCC (V) • AVCC = 3.0 V to 5.5 V • Active mode • Sleep mode (When MA2 = 0 in SYSCR2) 2000 1250 78.125 2.7 4.0 5.5 VCC (V) • AVCC = 3.0 V to 5.5 V • Active mode • Sleep mode (When MA2 = 1 in SYSCR2) Rev. 6.00 Mar. 24, 2006 Page 330 of 412 REJ09B0142-0600 2.7 4.0 5.5 • AVCC = 3.0 V to 5.
Section 20 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range: φ (MHz) 16.0 10.0 2.0 3.0 4.0 5.5 AVCC (V) • VCC = 2.7 V to 5.5 V • Active mode • Sleep mode 20.3.2 DC Characteristics Table 20.10 DC Characteristics (1) VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C unless otherwise indicated. Values Item Symbol Input high VIH voltage Applicable Pins Test Condition VCC = 4.0 V to 5.
Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Input low voltage VIL Output high voltage VOH Min Typ Max Unit VCC = 4.0 V to 5.5 V RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV –0.3 — VCC × 0.2 V –0.3 — VCC × 0.1 V RXD, SCL, SDA, P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76, P80 to P87, PB0 to PB7 VCC = 4.0 V to 5.5 V –0.3 — VCC × 0.3 V –0.3 — VCC × 0.2 V OSC1 VCC = 4.0 V to 5.5 V –0.3 — 0.
Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Output low voltage VOL P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76 P80 to P87 Test Condition Min Typ Max Unit — 0.6 V — — 0.4 V VCC = 4.0 V to 5.5 V — — 1.5 V — 1.0 V — 0.4 V VCC = 4.0 V to 5.5 V — Notes IOL = 1.6 mA IOL = 0.4 mA IOL = 20.0 mA VCC = 4.0 V to 5.5 V — IOL = 10.0 mA VCC = 4.0 V to 5.5 V — IOL = 1.6 mA IOL = 0.4 mA — — 0.4 V VCC = 4.0 to — — 0.6 V — — 0.
Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes Input capacitance Cin All input pins except power supply pins f = 1 MHz, VIN = 0.0 V, Ta = 25°C — — 15.0 pF Active mode supply current IOPE1 VCC Active mode 1 VCC = 5.0 V, fOSC = 16 MHz — 15.0 22.5 mA * Active mode 1 VCC = 3.0 V, fOSC = 10 MHz — 8.0 — mA * Reference value Active mode 2 VCC = 5.0 V, fOSC = 16 MHz — 1.8 2.7 mA * Active mode 2 VCC = 3.
Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit RAM data retaining voltage VRAM VCC 2.0 — — V Note: Pin states during supply current measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Section 20 Electrical Characteristics Table 20.10 DC Characteristics (2) VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated. Applicable Values Item Symbol Pins Test Condition Min Typ Max Unit Allowable output low current (per pin) IOL Output pins except port 8, SCL, and SDA VCC = 4.0 V to 5.5 V — — 2.0 mA — — 20.0 mA Port 8 Allowable output low current (total) ∑IOL Port 8 — — 10.0 mA SCL and SDA — — 6.
Section 20 Electrical Characteristics 20.3.3 AC Characteristics Table 20.11 AC Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Applicable Values Reference Item Symbol Pins Test Condition Min Typ Max Unit Figure System clock oscillation frequency fOSC OSC1, OSC2 VCC = 4.0 V to 5.5 V 2.0 — 16.0 MHz * System clock (φ) cycle time tcyc 1 — 64 tOSC * — — 12.8 µs 2.0 10.0 Subclock oscillation fW frequency X1, X2 — 32.
Section 20 Electrical Characteristics Applicable Values Reference Item Symbol Pins Test Condition Min Typ Max Unit Figure RES pin low width tREL RES At power-on and in modes other than those below trc — — ms Figure 20.
Section 20 Electrical Characteristics Table 20.
Section 20 Electrical Characteristics Table 20.13 Serial Interface (SCI3) Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Applicable Item Input clock Asynchronous cycle Clocked synchronous Symbol Pins tScyc SCK3 Input clock pulse width tSCKW SCK3 Transmit data delay time (clocked synchronous) tTXD TXD Receive data setup time (clocked synchronous) tRXS Receive data hold time (clocked synchronous) tRXH RXD RXD Rev. 6.00 Mar.
Section 20 Electrical Characteristics 20.3.4 A/D Converter Characteristics Table 20.14 A/D Converter Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified. Item Symbol Applicable Test Pins Condition Values Reference Min Typ Max Unit Figure Analog power supply AVCC voltage AVCC 3.0 VCC 5.5 V * Analog input voltage AN0 to AN7 VSS – 0.3 — AVCC + 0.3 V — — 2.0 mA AVIN Analog power supply AIOPE current AVCC AVCC = 5.
Section 20 Electrical Characteristics Applicable Test Item Symbol Pins Conversion time (single mode) Values Reference Condition Min Typ Max Unit AVCC = 4.0 V to 5.5 V 134 — — tcyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Figure Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2.
Section 20 Electrical Characteristics 20.4 Operation Timing t OSC VIH OSC1 VIL t CPH t CPL t CPf t CPr Figure 20.1 System Clock Input Timing VCC VCC × 0.7 OSC1 tREL RES VIL VIL tREL Figure 20.2 RES Low Width Timing NMI IRQ0 to IRQ3 WKP0 to WKP5 ADTRG TMCI FTIOA to FTIOD TMCIV, TMRIV TRGV VIH VIL t IL t IH Figure 20.3 Input Timing Rev. 6.00 Mar.
Section 20 Electrical Characteristics VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL P* tSDAS tSCL tSDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 20.4 I2C Bus Interface Input/Output Timing t SCKW SCK3 t Scyc Figure 20.5 SCK3 Input Clock Timing Rev. 6.00 Mar.
Section 20 Electrical Characteristics t Scyc VIH or VOH * VIL or VOL * SCK3 t TXD VOH* TXD (transmit data) VOL * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high: VOH = 2.0 V Output low: VOL = 0.8 V Load conditions are shown in figure 20.8. Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode 1/fSCL tsf tSCLH tSCLL tsp SCL tSTAS tSDAH tSTAH tSTOS tSDAS tsr SDA (in) tBUF tAA tDH SDA (out) Figure 20.7 EEPROM Bus Timing Rev. 6.
Section 20 Electrical Characteristics 20.5 Output Load Condition VCC 2.4 kΩ LSI output pin 30 pF 12 k Ω Figure 20.8 Output Load Circuit Rev. 6.00 Mar.
Appendix Appendix A Instruction Set A.
Appendix Symbol Description ⊕ Logical exclusive OR of the operands on both sides ¬ NOT (logical complement) ( ), < > Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7).
Appendix Table A.1 Instruction Set 1. Data transfer instructions Condition Code MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) → Rd8 — — MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) → Rd8 — — MOV.B @ERs+, Rd B @ERs → Rd8 ERs32+1 → ERs32 — — MOV.B @aa:8, Rd B 2 @aa:8 → Rd8 — — MOV.B @aa:16, Rd B 4 @aa:16 → Rd8 — — MOV.B @aa:24, Rd B 6 @aa:24 → Rd8 — — MOV.B Rs, @ERd B Rs8 → @ERd — — MOV.B Rs, @(d:16, ERd) B 4 Rs8 → @(d:16, ERd) — — MOV.
Appendix No. of States*1 Condition Code — — @(d:24, ERs) → ERd32 — — @ERs → ERd32 ERs32+4 → ERs32 — — 6 @aa:16 → ERd32 — — 8 @aa:24 → ERd32 — — ERs32 → @ERd — — ERs32 → @(d:16, ERd) — — ERs32 → @(d:24, ERd) — — ERd32–4 → ERd32 ERs32 → @ERd — — 6 ERs32 → @aa:16 — — 8 ERs32 → @aa:24 — — 0 — 0 — POP POP.W Rn W 2 @SP → Rn16 SP+2 → SP — — POP.L ERn L 4 @SP → ERn32 SP+4 → SP — — 0 — PUSH PUSH.W Rn W 2 SP–2 → SP Rn16 → @SP — — 0 — PUSH.
Appendix 2. Arithmetic instructions No. of States*1 Condition Code Z V C ↔ ↔ — (2) ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ERd32+ERs32 → ERd32 — (2) ↔ ↔ (3) ↔ ↔ Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ERd32 2 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ADDS ADDS.L #1, ERd L 2 ERd32+1 → ERd32 — — — — — — 2 ADDS.L #2, ERd L 2 ERd32+2 → ERd32 — — — — — — 2 ADDS.L #4, ERd L 2 ERd32+4 → ERd32 — — — — — — 2 INC.B Rd B 2 Rd8+1 → Rd8 — — INC.W #1, Rd W 2 Rd16+1 → Rd16 — — INC.
Appendix No. of States*1 Condition Code Advanced V C ERd32–1 → ERd32 — — L 2 ERd32–2 → ERd32 — — ↔ ↔ — 2 DAS.Rd B 2 Rd8 decimal adjust → Rd8 — * ↔ ↔ ↔ 2 DEC.L #2, ERd ↔ ↔ ↔ — * — 2 B 2 Rd8 × Rs8 → Rd16 (unsigned multiplication) — — — — — — 14 W 2 Rd16 × Rs16 → ERd32 (unsigned multiplication) — — — — — — 22 B 4 Rd8 × Rs8 → Rd16 (signed multiplication) — — ↔ W 4 Rd16 × Rs16 → ERd32 (signed multiplication) — — B 2 W DIVXU DIVXU. B Rs, Rd DIVXU.
Appendix No. of States*1 L 0–ERd32 → ERd32 2 — EXTU EXTU.W Rd W 0 → ( of Rd16) 2 — — 0 L 0 → ( of ERd32) 2 — — 0 W ( of Rd16) → ( of Rd16) 2 — — L ( of ERd32) → ( of ERd32) 2 — — Advanced NEG.L ERd Normal ↔ ↔ ↔ — ↔ ↔ ↔ ↔ ↔ ↔ 2 ↔ ↔ ↔ C ↔ ↔ ↔ ↔ W 0–Rd16 → Rd16 EXTS.L ERd V 2 0 — 2 ↔ NEG.W Rd EXTS EXTS.W Rd Z 0 — 2 ↔ — 0 — 2 ↔ H 2 EXTU.L ERd N ↔ I B 0–Rd8 → Rd8 NEG NEG.
Appendix 3. Logic instructions AND.B Rs, Rd B AND.W #xx:16, Rd W 4 AND.W Rs, Rd W AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W 4 OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W 4 XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L 4 ERd32⊕ERs32 → ERd32 — — NOT.B Rd B 2 ¬ Rd8 → Rd8 — — NOT.W Rd W 2 ¬ Rd16 → Rd16 — — NOT.
Appendix 4. Shift instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 ROTXR ROTXR.
Appendix 5.
Appendix B BLD #xx:3, @aa:8 B BILD BILD #xx:3, Rd BST BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BST #xx:3, @aa:8 B BIST BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd B BAND #xx:3, @ERd B BAND #xx:3, @aa:8 B BIAND BIAND #xx:3, Rd BOR B B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #
Appendix 6. Branching instructions Bcc No.
Appendix JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — No.
Appendix 7. System control instructions No. of States*1 Condition Code Advanced — CCR ← @SP+ PC ← @SP+ — Transition to powerdown state @aa:16 → CCR 8 @aa:24 → CCR — — — — — — 8 6 CCR → @aa:16 — — — — — — 8 8 CCR → @aa:24 — — — — — — 10 W STC CCR, @aa:24 W ANDC ANDC #xx:8, CCR B 2 CCR∧#xx:8 → CCR B 2 CCR∨#xx:8 → CCR B 2 CCR⊕#xx:8 → CCR 2 PC ← PC+2 ↔ ↔ ↔ STC CCR, @aa:16 REJ09B0142-0600 ↔ ERd32–2 → ERd32 CCR → @ERd 4 Rev. 6.00 Mar.
Appendix 8. Block transfer instructions EEPMOV No. of States*1 H N Z V C Normal — @@aa @(d, PC) I EEPMOV. B — 4 if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next — — — — — — 8+ 4n*2 EEPMOV.
REJ09B0142-0600 Rev. 6.00 Mar. 24, 2006 Page 362 of 412 MULXU 5 SUBX OR XOR AND MOV C D E F BILD BIST BLD BST TRAPA BEQ B BIAND BAND AND RTE BNE CMP BIXOR BXOR XOR BSR BCS A BIOR BOR OR RTS BCC MOV.B Table A-2 (2) LDC 7 ADDX BTST DIVXU BLS AND.B ANDC 6 9 BCLR MULXU BHI XOR.B XORC 5 ADD BNOT DIVXU BRN OR.
BRN ADD ADD SUBS DAS BRA MOV MOV 1B 1F 58 79 7A NOT 17 DEC ROTXR 13 1 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 CMP CMP BHI 2 SUB SUB BLS OR OR XOR XOR BCS AND AND BEQ BVC SUB 9 BVS NEG NOT DEC ROTR ROTXR DEC ROTL ADDS SLEEP 8 ROTXL EXTU INC 7 SHAR BNE 6 SHLR EXTU INC 5 SHAL BCC LDC/STC 4 SHLL 3 1st byte 2nd byte AH AL BH BL BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Table A-2 Tabl
REJ09B0142-0600 Rev. 6.00 Mar. 24, 2006 Page 364 of 412 DIVXS 3 BSET 7Faa7 * 2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM — Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. See section 19.1, Register Addresses (Address Order). Rev. 6.00 Mar.
Appendix Table A.4 Number of Cycles in Each Instruction Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N BTST BXOR CMP BTST #xx:3, Rd 1 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @ERd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 BXOR #xx:3, @ERd 2 1 BXOR #xx:3, @aa:8 2 1 CMP.B #xx:8, Rd 1 CMP.B Rs, Rd 1 CMP.W #xx:16, Rd 2 CMP.W Rs, Rd 1 CMP.L #xx:32, ERd 3 CMP.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N INC JMP JSR LDC MOV Stack K INC.B Rd 1 INC.W #1/2, Rd 1 INC.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N MOV MOV.B Rs, @aa:16 2 1 MOV.B Rs, @aa:24 3 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 1 MOV.W @(d:16,ERs), Rd 2 1 MOV.W @(d:24,ERs), Rd 4 1 MOV.W @ERs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W @aa:24, Rd 3 1 MOV.W Rs, @ERd 1 1 MOV.W Rs, @(d:16,ERd) 2 1 MOV.W Rs, @(d:24,ERd) 4 1 MOV.W Rs, @-ERd 1 1 MOV.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N MULXS MULXU NEG K MULXS.B Rs, Rd 2 12 MULXS.W Rs, ERd 2 20 MULXU.B Rs, Rd 1 12 MULXU.W Rs, ERd 1 20 NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 NOP NOP 1 NOT NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 OR Stack OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 OR.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N ROTXR RTE ROTXR.B Rd 1 1 ROTXR.L ERd 1 RTE 2 2 2 1 2 RTS 2 SHAL SHAL.B Rd 1 SHAL.W Rd 1 SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL K ROTXR.W Rd RTS SHAR Stack SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 SHLR.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J K L M N SUBX SUBX #xx:8, Rd 1 SUBX. Rs, Rd 1 1 2 TRAPA TRAPA #xx:2 2 XOR XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 XORC Stack 4 Notes: 1. n:specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2.
Appendix A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes @@aa:8 — — — — — — — WL — BWL BWL — @(d:16.PC) — — — @aa:24 — — — B @aa:16 — — — @aa:8 @ERn+/@ERn @(d:24.ERn) @ERn BWL BWL BWL BWL BWL BWL — — — — — — — — — — — — @(d:8.PC) Data MOV transfer POP, PUSH instructions MOVFPE, Rn Instructions #xx Functions @(d:16.
Appendix Appendix B I/O Port Block Diagrams B.1 I/O Port Block RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev. 6.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P16 to P14) Rev. 6.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PDR PCR [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.3 Port 1 Block Diagram (P12, P11) Rev. 6.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR Timer A TMOW [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.4 Port 1 Block Diagram (P10) Rev. 6.00 Mar.
Appendix Internal data bus SBY PMR PDR PCR SCI3 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.5 Port 2 Block Diagram (P22) Rev. 6.00 Mar.
Appendix SBY Internal data bus PDR PCR SCI3 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.6 Port 2 Block Diagram (P21) Rev. 6.00 Mar.
Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.7 Port 2 Block Diagram (P20) Rev. 6.00 Mar.
Appendix Internal data bus SBY PDR PCR IIC ICE SDAO/SCLO SDAI/SCLI [Legend] PDR: Port data register PCR: Port control register Figure B.8 Port 5 Block Diagram (P57, P56)* Note: * Not included in H8/3664N. Rev. 6.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.9 Port 5 Block Diagram (P55) Rev. 6.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.10 Port 5 Block Diagram (P54 to P50) Rev. 6.00 Mar.
Appendix Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.11 Port 7 Block Diagram (P76) Rev. 6.00 Mar.
Appendix Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.12 Port 7 Block Diagram (P75) Rev. 6.00 Mar.
Appendix Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.13 Port 7 Block Diagram (P74) Rev. 6.00 Mar.
Appendix Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.14 Port 8 Block Diagram (P87 to P85) Rev. 6.00 Mar.
Appendix Internal data bus SBY Timer W Output control signals A to D PDR PCR FTIOA FTIOB FTIOC FTIOD [Legend] PDR: Port data register PCR: Port control register Figure B.15 Port 8 Block Diagram (P84 to P81) Rev. 6.00 Mar.
Appendix Internal data bus SBY PDR PCR Timer W FTCI [Legend] PDR: Port data register PCR: Port control register Figure B.16 Port 8 Block Diagram (P80) Rev. 6.00 Mar.
Appendix Internal data bus A/D converter CH3 to CH0 DEC VIN Figure B.17 Port B Block Diagram (PB7 to PB0) Rev. 6.00 Mar.
Appendix B.
Appendix Appendix C Product Code Lineup Product Type H8/3664 Model Marking Package Code Flash memory Standard HD64N3664FP version with product EEPROM HD64N3664FP LQFP-64 (FP-64E) Flash memory Standard HD64F3664FP version product HD64F3664H HD64F3664FP LQFP-64 (FP-64E) HD64F3664H QFP-64 (FP-64A) HD64F3664FX HD64F3664FX LQFP-48 (FP-48F) HD64F3664FY HD64F3664FY LQFP-48 (FP-48B) HD64F3664BP HD64F3664BP SDIP-42 (DP-42S) Standard HD6433664FP product HD6433664H HD6433664 (***) FP LQFP-64 (FP
Appendix Product Type H8/3660 Mask ROM version Product Code Model Marking Package Code Standard HD6433660FP product HD6433660H HD6433660 (***) FP LQFP-64 (FP-64E) HD6433660 (***) H QFP-64 (FP-64A) HD6433660FX HD6433660 (***) FX LQFP-48 (FP-48F) HD6433660FY HD6433660 (***) FY LQFP-48 (FP-48B) HD6433660BP HD6433660 (***) BP SDIP-42 (DP-42S) [Legend] (***): ROM code Rev. 6.00 Mar.
Appendix Appendix D Package Dimensions The package dimensions that are shows in the Renesas Semiconductor Packages Data Book have priority. 12.0 ± 0.2 Unit: mm 10 48 33 32 0.5 12.0 ± 0.2 49 64 17 0.10 *Dimension including the plating thickness Base material dimension 1.70 Max 1.25 1.45 0.08 M 0.10 ± 0.10 *0.22 ± 0.05 0.20 ± 0.04 16 *0.17 ± 0.05 0.15 ± 0.04 1 1.0 0° − 8° 0.5 ± 0.2 Package Code JEDEC EIAJ Mass (reference value) FP-64E − Conforms 0.4 g Figure D.
Appendix Unit: mm 17.2 ± 0.3 14 33 48 32 0.8 17.2 ± 0.3 49 64 17 1 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 3.05 Max 1.0 2.70 0.15 M 0.10 +0.15 - 0.10 *0.37 ± 0.08 0.35 ± 0.06 16 1.6 0° − 8° 0.8 ± 0.3 Package Code JEDEC EIAJ Mass (reference value) Figure D.2 FP-64A Package Dimensions Rev. 6.00 Mar. 24, 2006 Page 398 of 412 REJ09B0142-0600 FP-64A − Conforms 1.
Appendix 12.0 ± 0.2 10 Unit: mm 25 37 24 48 13 1 0.65 12.0 ± 0.2 36 12 1.425 0.50 ± 0.1 0.10 *Dimension including the plating thickness Base material dimension 0.1 ± 0.05 *0.17 ± 0.05 0.15 ± 0.04 1.0 1.65 Max 0.13 M 1.45 *0.32 ± 0.05 0.30 ± 0.04 0° – 8 ° Package Code JEDEC EIAJ Mass (reference value) FP-48F — — 0.4 g Figure D.3 FP-48F Package Dimensions Rev. 6.00 Mar.
Appendix 9.0 ± 0.2 7 0.5 25 37 24 48 13 1 12 *0.22 ± 0.05 0.20 ± 0.04 1.70 Max 0.10 ± 0.07 0.75 *0.17 ± 0.05 0.15 ± 0.04 0.08 M 1.40 9.0 ± 0.2 36 Unit: mm 0.08 1.0 0˚ – 8˚ 0.5 ± 0.1 Package Code JEDEC JEITA Mass (reference value) *Dimension including the plating thickness Base material dimension FP-48B — — 0.2 g Figure D.4 FP-48B Package Dimensions Unit: mm 37.3 38.6 Max 22 14.0 14.6 Max 42 21 5.10 Max 1.0 1.78 ± 0.25 0.48 ± 0.10 0.51 Min 1.38 Max 2.54 Min 1 15.24 0.
Appendix Appendix E EEPROM Stacked-Structure Cross-Sectional View Figure E.1 EEPROM Stacked-Structure Cross-Sectional View Rev. 6.00 Mar.
Appendix Rev. 6.00 Mar.
Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Preface vi, vii Amended When using the on-chip emulator (E7, E8) for H8/3664 program development and debugging, the following restrictions must be noted (the on-chip debugging emulator (E7) can also be used). Notes 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3.
Item Page Revision (See Manual for Details) 6.1.1 System Control Register 1 (SYSCR1) 85 Amended Bit Bit Name Description 3 NESEL Noise Elimination Sampling Frequency Select The subclock pulse generator generates the watch clock signal (φW) and the system clock pulse generator generates the oscillator clock (φOSC). This bit selects the sampling frequency of the oscillator clock when the watch clock signal (φW) is sampled. When φOSC = 4 to 16 MHz, clear NESEL to 0.
Item Page Revision (See Manual for Details) 9.5.3 Pin Functions 136 • P83/FTIOC Pin Amended Register TMRW Bit Name PWMC IOC2 IOC1 IOC0 PCR83 Pin Function Setting Value 0 0 0 0 0 P83 input/FTIOC input pin 1 P83 output/FTIOC input pin 0 0 1 X FTIOC output pin 0 1 X X FTIOC output pin 1 X X 0 P83 input/FTIOC input pin 1 P83 output/FTIOC input pin X X X X PWM output pin 1 9.5.
Item Page Revision (See Manual for Details) 15.5 Usage Notes 271 to Added. 274 • Notes on WAIT Function • Notes on TRS Bit Setting and ICDR Register Access 16.3.1 A/D Data Registers A to D 278 (ADDRA to ADDRD) Table 20.2 DC Characteristics (1) 314 Amended … Therefore, byte access to ADDR should be done by reading the upper byte first then the lower one. Word access is also possible. ADDR is initialized to H'0000.
Item Page Revision (See Manual for Details) Table 20.10 DC Characteristics (1) 331, 332 Amended Values Item Applicable Pins Test Condition Min Input high voltage PB0 to PB7 VCC = 4.0 V to 5.5 V VCC × 0.7 Input low voltage P50 to P57*, P74 to P76, P80 to P87, PB0 to PB7 AVCC = 3.3 V to 5.5 V VCC × 0.8 Pb0 to PB7 –0.3 AVCC = 4.0 V to 5.5 V –0.3 AVCC = 3.3 V to 5.5 V –0.3 Amended 2.
Rev. 6.00 Mar.
Index A A/D converter ......................................... 275 Sample-and-hold circuit...................... 282 Scan mode........................................... 281 Single mode ........................................ 281 Absolute maximum ratings..................... 311 Address break ........................................... 67 Addressing modes..................................... 35 Absolute address................................... 37 Immediate .............................................
Software protection............................. 109 G General registers ....................................... 18 I I/O ports.................................................. 115 I/O port block diagrams ...................... 377 I2C bus interface (IIC) ............................ 233 Acknowledge...................................... 250 Clock synchronous serial format ........ 259 General call address............................ 247 I2C bus data formats ...........................
GRB............................ 171, 302, 305, 308 GRC............................ 171, 302, 305, 308 GRD............................ 171, 302, 305, 308 ICCR........................... 242, 303, 306, 309 ICDR........................... 236, 303, 306, 309 ICMR.......................... 239, 303, 306, 309 ICSR ........................... 245, 303, 306, 309 IEGR1........................... 53, 304, 307, 310 IEGR2........................... 54, 304, 307, 310 IENR1...........................
V W Vector address .......................................... 52 Watchdog timer....................................... 191 Rev. 6.00 Mar.
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/3664 Group Publication Date: 1st Edition, Mar, 2000 Rev.6.00, Mar. 24, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8/3664 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0142-0600
