HD151TS207SS Mother Board Clock Generator for Intel P4+ Chipset (Springdale) REJ03D0006-0100Z Preliminary Rev.1.00 Apr.25.2003 Description The HD151TS207SS is Intel CK409T type high-performance, low-skew, low-jitter, PC motherboard clock generator. It is specifically designed for Intel Pentium®4+ chipset.
HD151TS207SS Key Specifications • • • • • Supply Voltages: VDD = 3.3 V±5% CPU clock cycle to cycle jitter = |125ps| (SSC Disabled) CPU clock group Skew = 100ps 3V66 clock group Skew = 250psmax PCI clock group Skew = 500psmax Rev.1.00, Apr.25.
HD151TS207SS Pin Arrangement REF0 1 56 FS_B REF1 2 55 VDD_A VDD_REF 3 54 VSS_A 53 VSS_IREF XTAL_IN 4 XTAL_OUT 5 52 IREF VSS_REF 6 51 FS_A FS2/PCIF_0 7 50 TEST_CLK# FS4/PCIF_1 8 49 PCI_STOP# PCIF_2 9 48 VDD_CPU VDD_PCI 10 47 CPU_2 VSS_PCI 11 46 CPU_2# MODE/PCI_0 12 45 VSS_CPU PCI_1 13 44 CPU_1 PCI_2 14 43 CPU_1# PCI_3 15 42 VDD_CPU VDD_PCI 16 41 CPU_0 VSS_PCI 17 40 CPU_0# 39 VSS_SRC SEL100_200/PCI_4 18 38 SRC SEL33_25/PCI_5 19 37 SRC# PCI_6 20 36 VDD_SRC PWRDWN#/SAFE_F
HD151TS207SS Pin Descriptions Pin name No. Type Description VSS_A 54 Ground Ground for PLL VSS_CPU 45 Ground for outputs VSS_IREF 53 Ground for current reference VSS_SRC 39 Ground for outputs VSS_3V66 25 VSS_PCI 11, 17 VSS_REF 6 VSS_48 33 VDD_A 55 VDD_CPU 42, 48 VDD_SRC 36 VDD_3V66 24 VDD_PCI 10, 16 VDD_REF 3 VDD_48 34 REF0 1 REF1 2 XTAL_IN Power 3.3 V Power Supply for PLL 3.3 V Power Supply for outputs OUTPUT 3.3 V 14.318 MHz reference clock. 4 INPUT 14.
HD151TS207SS Pin Descriptions (cont.) Pin name No. Type Description PWRDWN#/ SAFE_F# 21 INPUT PULL–UP* PWRDWN# / SAFE_F# selectable input. Default is PWRDWN# input. Byte15[5] = “1” : SAFE_F# input. PWRDWN# is all clocks stop pin. Asynchronous active “Low” input. When asserted low, all output clocks are disabled. SAFE_F# is active “Low” input. When SAFE_F# is “Low” ,frequency mode is changed to the predefined frequency mode. 3V66_0/RESET# 22 OUTPUT 3V66 / Watchdog RESET# selectable output.
HD151TS207SS Block Diagram 3.3 V VDD_48 VSS_48 3.3 V VDD_A VSS_A 6× 3.3V VDD 6×VSS VSS_IREF IREF REF[1:0] (14.318MHz) XTAL 14.
HD151TS207SS I2C Controlled Register Bit Map Byte0 Control Register Bit Description 7 Contents Type Default Reserved R 0 6 Reserved R 0 5 Reserved R 0 4 Reserved R 0 3 PCI_Stop Reflects the current value of the external PCI_STOP# pin R X 2 Reserved R X 1 FS_B Reflects the value of the FS_B pin sampled on power up 0 = FS_B Low at power up 1 = FS_B High at power up R X 0 FS_A Reflects the value of the FS_A pin sampled on power up 0 = FS_A Low at power up 1 = FS_A High at p
HD151TS207SS I2C Controlled Register Bit Map (cont.) Table3 FS_A and FS_B pin Input level Logic Level Min Voltage Max Voltage 0 (Low) 0.35V 1 (High) 0.
HD151TS207SS I2C Controlled Register Bit Map (cont.) Table4 CPU Clock Power Management Truth Table Signal Pin PWRDWN# PWRDWN# Tristate Bit Byte2[5:3] Non-Stop Outputs Byte1[5:3] = 1 CPU[2:0] 1 X Running CPU[2:0] 0 0 Driven @ Iref x2 CPU[2:0] 0 1 Tristate Note: Note See Note1 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA, Iref x2 = 4.6 mA (Voh @Z: 0.
HD151TS207SS I2C Controlled Register Bit Map (cont.
HD151TS207SS I2C Controlled Register Bit Map (cont.
HD151TS207SS I2C Controlled Register Bit Map (cont.
HD151TS207SS I2C Controlled Register Bit Map (cont.) Table6 Clock Frequency Function Table No. FS_4 FS_3 FS_2 FS_A FS_B CPU [MHz] SRC [MHz] 3V66 [MHz] PCI [MHz] B9[5] B9[4] B9[3] B9[2] B9[1] 0 0 0 0 0 0 100.02 100.02 66.68 33.34 1 0 0 0 0 1 200.03 100.02 66.68 33.34 2 0 0 0 1 0 133.36 100.02 66.68 33.34 3 0 0 0 1 1 166.69 100.02 66.68 33.34 4 0 0 1 0 0 200.03 100.02 66.68 33.34 5 0 0 1 0 1 400.07 100.02 66.68 33.
HD151TS207SS I2C Controlled Register Bit Map (cont.) Byte10 Control Register Bit Description Contents Type Default 7 SSC Spread Select Bit[2:0] Bit[2:0] = 000 = –0.500%, 100 = ±0.250% 001 = –0.750%, 101 = ±0.375% 010 = –1.000%, 110 = ±0.500% 011 = –1.500%, 111 = ±0.
HD151TS207SS I2C Controlled Register Bit Map (cont.
HD151TS207SS I2C Controlled Register Bit Map (cont.) Byte14 Control Register Bit Description 7 Reserved 6 PLL1 M1 Divider Control Bit6 5 Type Default Note R/W 0 M1[6] R/W 0 See Note 1 PLL1 M1 Divider Control Bit5 M1[5] R/W 0 4 PLL1 M1 Divider Control Bit4 M1[4] R/W 1 3 PLL1 M1 Divider Control Bit3 M1[3] R/W 0 2 PLL1 M1 Divider Control Bit2 M1[2] R/W 0 1 PLL1 M1 Divider Control Bit1 M1[1] R/W 1 0 PLL1 M1 Divider Control Bit0 M1[0] R/W 0 Note: Contents 1.
HD151TS207SS I2C Controlled Register Bit Map (cont.
HD151TS207SS I2C Controlled Register Bit Map (cont.) Byte18 Control Register Bit Description Contents Type Default Note 7 VCO2 Frequency Control Bit7 R/W 0 6 VCO2 Frequency Control Bit6 These bits are 10MHz digit of VCO2 frequency. 0000 = 0, 0001 = 1 ….
HD151TS207SS I2C Controlled Register Bit Map (cont.) Byte19 Control Register Bit Description Contents Type Default 7 VCO2 Frequency Read Bit15 R 0 6 VCO2 Frequency Read Bit14 R 0 5 VCO2 Frequency Read Bit13 Calculation result of VCO2 frequency. 100 MHz digit 0000 = 0, 0001 = 1 …. 1001 = 9 R 0 4 VCO2 Frequency Read Bit12 R 0 3 VCO2 Frequency Read Bit11 R 0 2 VCO2 Frequency Read Bit10 1 VCO2 Frequency Read Bit9 0 VCO2 Frequency Read Bit8 Calculation result of VCO2 frequency.
HD151TS207SS I2C Controlled Register Bit Map (cont.) Byte22 Control Register Bit Description Contents Type Default 7 CPU Frequency Read Bit7 R 0 6 CPU Frequency Read Bit6 Calculation result of CPU frequency. 1 MHz digit 0000 = 0, 0001 = 1 …. 1001 = 9 R 0 5 CPU Frequency Read Bit5 R 0 4 CPU Frequency Read Bit4 R 0 3 CPU Frequency Read Bit3 R 0 2 CPU Frequency Read Bit2 R 0 1 CPU Frequency Read Bit1 R 0 0 CPU Frequency Read Bit0 R 0 Calculation result of CPU frequency.
HD151TS207SS I2C Controlled Register Bit Map (cont.
HD151TS207SS I2C Controlled Register Bit Map (cont.) Byte26 Control Register Bit Description Contents Type Default Note 7 PCIF / PCI Clock Skew2 Control Bit3 R/W 0 6 PCIF / PCI Clock Skew2 Control Bit2 R/W 0 See Note 1 5 PCIF / PCI Clock Skew2 Control Bit1 R/W 0 4 PCIF / PCI Clock Skew2 Control Bit0 Skew2 is “Late” Skew that is Delay Time from “Normal” Skew1. 0000 = +0.0ns, 1000 = +3.2ns 0001 = +0.4ns, 1001 = +3.6ns 0010 = +0.8ns, 1010 = +4.0ns 0011 = +1.2ns, 1011 = +4.4ns 0100 = +1.
HD151TS207SS I2C Controlled Register Bit Map (cont.
HD151TS207SS Clock Stop Timing Diagram PCI_STOP# Assertion/De-assersion PCI_STOP# PCI_F Low PCI SRC (Stoppable) 6× Iref (Controled by Byte2[6]) SRC (Stoppable) Tristate (Controled by Byte2[6]) SRC# (Stoppable) Tristate PCI_STOP# Assertion/De-assertion Waveforms PWRDWN# Assertion/De-assersion < 1.
HD151TS207SS Renesas clock generator I2C Serial Interface Operation 1. Write mode 1.1 Controller (host) sends a start bit. 1.2 Controller (host) sends the write address D2 (h). 1.3 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”). 1.4 Controller (host) sends a begin byte M. 1.5 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”). 1.6 Controller (host) sends a byte count N. 1.7 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”). 1.
HD151TS207SS Renesas clock generator I2C Serial Interface Operation (cont.) 2. Read mode 2.1 Controller (host) sends a start bit. 2.2 Controller (host) sends the write address D2 (h). 2.3 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”). 2.4 Controller (host) sends a begin byte M. 2.5 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”). 2.6 Controller (host) sends a restart bit. 2.7 Controller (host) sends the read address D3 (h). 2.
HD151TS207SS Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VDD –0.5 to 4.6 V Input voltage VI –0.5 to 4.6 V Output voltage *1 VO –0.5 to VDD +0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VDD 0.
HD151TS207SS DC Electrical Characteristics / Serial Input Port Ta = 0°C to 70°C, VDD = 3.3 V Typ *1 Max Unit 0.8 V VIH 2.0 V Input Current II –50 +50 µA VI = 0 V or 3.465 V, VDD = 3.465 V Input capacitance CI 10 pF SDATA & SCLK Item Symbol Min Input Low Voltage VIL Input High Voltage Note: Test Conditions 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
HD151TS207SS DC Electrical Characteristics CPU/CPU# Clock Ta = 0°C to 70°C, VDD = 3.3 V, Iref = 475 Ω Typ *1 Item Symbol Min Output voltage VO IO 3000 Output Current Output resistance Max Unit Test Conditions 1.20 V Rp = 49.9 Ω, VDD = 3.3 V I(nom) * mA VDD = 3.3 V Ω VO = 1.2 V 2 Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditionaI (nom) is output current(Ioh) shown in below. 2. Ioh = VDD/(3Rr) = 3.
HD151TS207SS DC Electrical Characteristics SRC/SRC# Clock Ta = 0°C to 70°C, VDD = 3.3 V, Iref = 475 Ω Item Symbol Min Output voltage VO Output Current IO Output resistance Typ *1 Max Unit Test Conditions 1.20 V Rp = 49.9 Ω, VDD = 3.3 V I(nom) mA VDD = 3.3 V 3000 Ω VO = 1.2 V Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions 2. I(nom) is output current(Ioh) shown in below. Ioh = VDD/(3Rr) = 3.
HD151TS207SS DC Electrical Characteristics / 3V66 Buffer (CK409T Type5 Buffer) Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Min Typ *1 Max Unit Test Conditions Output Voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –33 mA VOH = 1.0 V IOL 30 mA VOL = 1.95 V Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
HD151TS207SS DC Electrical Characteristics / PCI & PCIF Clock (CK409T Type5 Buffer) Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Min Typ *1 Max Unit Test Conditions Output Voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –33 mA VOH = 1.0 V IOL 30 mA VOL = 1.95 V Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
HD151TS207SS DC Electrical Characteristics / USB & VCH 48MHz Clock (CK409T Type3A Buffer) Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Min Typ *1 Max Unit Test Conditions Output Voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –29 mA VOH = 1.0 V IOL 29 mA VOL = 1.95 V Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
HD151TS207SS DC Electrical Characteristics / DOT Clock (CK409T Type3B Buffer) Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Min Typ *1 Max Unit Test Conditions Output Voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –29 mA VOH = 1.0 V IOL 29 mA VOL = 1.95 V Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
HD151TS207SS DC Electrical Characteristics / REF Clock (CK409T Type5 Buffer) Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Min Typ *1 Max Unit Test Conditions Output Voltage VOH 3.1 V IOH = –1 mA, VDD = 3.3 V VOL 50 mV IOL = 1 mA, VDD = 3.3 V IOH –33 mA VOH = 1.0 V IOL 30 mA VOL = 1.95 V Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
HD151TS207SS Clock Out tcycle n+1 tcycle n t CCS = (tcycle n) - (tcycle n+1) Fig.1 Cycle to Cycle Jitter (3.3V Single Ended Clock Output) Clock Outx 1.5 V Clock Outy 1.5 V tskS Fig.2 Output Clock Skew (3.3V Single Ended Clock Output) RS = 33.2 Ω ZLT = ZLC = 50 Ω CPU LT TS207 RS = 33.2 Ω CPU# RI(ref) = 475 Ω LC RP = 49.9 Ω RP = 49.9 Ω CL = 2 pF Fig.3 Load Circuit for CPU/CPU# Rev.1.00, Apr.25.
HD151TS207SS Package Dimensions Unit : mm 18.40 29 7.50 56 1 28 10.35 Rev.1.00, Apr.25.2003, page 37 of 38 0.3 0.10(0.004) 0.2 0.635 2.6 0.25 0˚– 8˚ 0.5 0.
HD151TS207SS Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.