Technical information

9.2.Application Headers
Table 9-5 and belowTable 9-6 show the standard application header connections.
JA1
Pin Generic Header Name CPU board
Signal Name
Device
Pin
Pin Generic Header Name CPU board
Signal Name
Device
Pin
1 Regulated Supply (5V) --- --- 2 Regulated Supply 1 (Gnd) --- ---
3 Regulated Supply (3V3) --- --- 4 Regulated Supply 2 (Gnd) --- ---
5 Analogue Supply AVcc* 121 6 Analogue Supply AVss 123
7 Analogue Reference AVref* 125 8 ADTRG ADTRG* 87
9
AN0
AD0* 118 10 AD1 AN1 119
11
AN2
AD2 120 12 AD3 AN3 122
13
DAC0
DAC0* 127 14 DAC1 DA1* 128
15
IOPort
IO0* 49 16 IOPort IO1* 51
17
IOPort
IO2* 52 18 IOPort IO3* 53
19
IOPort
IO4* 54 20 IOPort IO5* 55
21
IOPort
IO6 59 22 IOPort IO7 60
23 Open drain IRQ3n IRQ3n* 87 24 IIC_EX --- ---
25 IIC_SDA SDA0 100 26 IIC_SCL SCL0 101
Table 9-5: JA1 Standard Generic Header
JA2
Pin Generic Header Name CPU board
Signal Name
Device
Pin
Pin Generic Header Name CPU board
Signal Name
Device
Pin
1 Open drain RESn 91 2 External Clock Input CON_EXTAL* 98
3 Open drain NMIn 61 4 Regulated Supply (Vss) --- ---
5 Open drain output WDT_OVF* 95 6 Serial Port TxD0* 52
7 Open drain WUP IRQ0 84 8 Serial Port RxD0* 51
9 Open drain IRQ1 85 10 Serial Port CLK0* 49
11 Up/down UD* 53 12 Serial Port Handshake --- ---
13 Motor control Up* 105 14 Motor control Un* 106
15 Motor control Vp* 56 16 Motor control Vn* 57
17 Motor control Wp* 55 18 Motor control Wn* 54
19 Output TIOCA0* 56 20 Output TIOCA2* 105
21 Input TIOCB0* 57 22 Input TIOCB2* 106
23 Open drain IRQ3n* 87 24 Tristate Control TRISTn 58
25 Reserved ---
---
26 Reserved ---
---
Table 9-6: JA2 Standard Generic Header
27