User`s manual

9.2.Application Headers
Table 9-5 and Table 9-6 below show the standard application header connections.
JA1
Pin Generic Header Name CPU board
Signal Name
Device
Pin
Pin Header Name CPU board
Signal Name
Device
Pin
1 Regulated Supply 1 5V 2 Regulated Supply 1 GROUND
3 Regulated Supply 2 3V3 4 Regulated Supply 2 GROUND
5 Analogue Supply AVcc 100,104 6 Analogue Supply AVss 102
7 Analogue Reference AVref 8 ADTRG ADTRG 57
9
ADC0 I0
AD0 97 10 ADC1 I1 AD1 98
11
ADC2 I2
AD2 99 12 ADC3 I3 AD3 101
13
DAC0
DAC0 14 DAC1 DAC1
15
IOPort
IO_0 36 16 IOPort IO_1 38
17
IOPort
IO_2 39 18 IOPort IO_3 40
19
IOPort
IO_4 41 20 IOPort IO_5 42
21
IOPort
IO_6 44 22 IOPort IO_7 45
23 Open drain IRQAEC IRQ3 53 24 I²C Bus - (3rd pin) IIC_EX 119
25
I²C Bus
IIC_SDA 114 26 I²C Bus IIC_SCL 117
Table 9-5: JA1 Standard Generic Header
JA2
Pin Generic Header Name CPU board
Signal Name
Device
Pin
Pin Header Name CPU board
Signal Name
Device
Pin
1 Open drain RESn 79 2 External Clock Input EXTAL 84*
3 Open drain NMIn 80 4 Regulated Supply 1 Vss1
5 Open drain output WDT_OVF 6 Serial Port SCIaTX 54
7 Open drain WUP IRQ0 47 8 Serial Port SCIaRX 55
9 Open drain IRQ1 49 10 Serial Port SCIaCK 56
11 Up/down MO_UD 28 12 Serial Port Handshake CTS/RTS 18
13 Motor control MO_Up 14 14 Motor control MO_Un 25
15 Motor control MO_Vp 15 16 Motor control MO_Vn 27
17 Motor control MO_Wp 17 18 Motor control MO_Wn 30
19 Output TMR0 69 20 Output TMR1 70
21 Input TRIGa 81 22 Input TRIGb 11
23 Open drain IRQ2 52 24 Tristate Control TRSTn 74
25 SPARE - 26 SPARE -
Table 9-6: JA2 Standard Generic Header
24