Hardware manual

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In the following lines, I'm not going to go into details about several registers which are need to
be set up properly, but I'll try to shortly explain mentioned above buffer operation mode,
synchronous operation mode, phase counting mode and cascaded operation. It is important to
understand all of them in proper way if we want to fully use this microcontroller. I don't
describe PWM because in general it uses standard PWM approach and two available modes
differ only in details.
 start with buffer operation mode. As pointed above, this mode is possibly only in channel 0
or 3. Switching on this option provides to situation in which TGRC and TGRD work as buffer
registers. The way how these two registers can be used depends on whether TGR works as
compare match or input capture. In the first situation, when a compare match occurs the value
in buffer register is transferred to the time general register. In the second situation, the value in
TGR is transferred to buffer register and at the same time the value in TGNT is transferred to
TGR.
Synchronous operation means that the values in a several TCNT counters can be cleared or
rewritten at the same time. This first operation we call synchronous clearing and second
synchronous presetting. Of course, in this mode, at begin we choose clearing operation for one
of the channels and then we set up other channels for synchronous clearing. The same we can
do for synchronous presetting.
Phase counting mode. This mode is little bit specific. Counter is incremented or decremented
according to differences in the phase of two external clocks connected to clock inputs pins for
channel 1, 2, 4 or 5. There are four different phase counting modes and they differ mostly on
how voltage levels should look like with regards to edges or eventually whether edges should be
rising or falling. Good graph examples for all methods are presented in documentation for
H8S/2638.
Cascaded operation is very easy to understand. In this mode we just virtually connect two
channels: 1 with 2 or 4 with 5. Thanks that, we get new 32-bit counter which consists from two
parts: lower and upper. Lower part is just counter from channel 2 or 5 and upper part is counter
from channel 1 or 4. In such configuration, upper part can be always incremented by overflow of
the lower part, and decremented by underflow of the lower part.