Hardware manual
28
Channels 0 and 3 are almost identical. This means both of them have the same interrupt
sources, the same number of general and buffer registers. Only one difference is with the
possibilities to set up the count clock. At this point I should mention that it is possible to count
clock's ticks in two different ways. First method is with use of internal clock. Here we have
several frequencies like: , /4, /16, /64, /256, /1024 and /4096. Second option is to
measure the ticks with a help of some external clock. These measurements we can do using
following pins: TCLKA, TCLKB, TCLKC and TCLKD.
Now, back to our channels 0 and 3. In the channel 0 we can set up count clock for four
frequencies: , /4, /16, /64 or we can measure it with help of all above mentioned pins. At
the same time channel 3 can have count clock with frequencies: , /4, /16, /64, /256,
/1024, /4096 or we can count ticks on the TLCKA pin. Both channels have four general
registers, from which two can also work as buffer registers. They have also four I/O pins on
which we can detect different edges: rising, falling or both of them. This is useful option during
counter clear. Counter clear is possible through TGR register compare match or by input capture
with properties mentioned above. During the compare match, output can take two values: 0 or
1 or it can be toggled. The output can be also set as PWM in one of two modes. All of these we
can set up separately and independent for each channel. Of course it is also possible to make
configuration of these channels that they will work in synchronous way. Channels 0 and 3 can
not work in phase count mode. Last one, what is important for us, are interrupt sources.
Interrupts can come from four compare match or input capture from
TGIOD and from TGI3A to TGI3D respectively for channel 0 and channel 3. It is also possible to
generate interrupt when the overflow occurs.
Channels 1, 2, 4 and 5 can all set up counter clock with frequencies: , /4, /16, /64 and it
is also possible to count external impulses with help of TCLKA. Additionally counter of channel 1
can have frequency: /256 and can use TCLKB. Channel 4 can have additional frequency for its
counter: /4 and can use TLCKC. Counter of channel 2 can be set up additionally with
frequency: /1024 and can use TCLKB and TCLKC. And at the end, channel 5 can have
additionally frequency for its counter clock: /256 and can use TCLKC and TCLKD. Above written
facts were the only differences between channels: 1, 2, 4 and 5. All next property like number of
general registers is the same for all channels and is equal to 2. All these channels have only two
I/O pins and counter clear can be done by TGR compare match or by input capture. In opposite
to channels 0 and 3, these can be set up to work in phase counting mode. The same as before,
they can have outputs with values: 0 or 1 or toggled. We can also use PWM output in one of two
modes. In addition it is possible to configure them to work in synchronous operation mode.
What is important, they can not provide buffer operations. Interrupts can be generated by
compare match or input capture on TGI1A and TGI1B for channel 1, TGI2A and TGI2B for
channel 2 and so one. Additionally it is possible to detect overflow and/or underflow and due to
its occurrence, generate interrupt.