Hardware manual
27
Independent interrupt vector address has big advantage, because in this case we don't have to
worry about identification of the source. All interrupts are controlled by the interrupt controller,
which has two control modes. The highest priority has NMI interrupt and this can not be
changed. To others interrupts we can assign eight priority levels. For external interrupts we can
detect falling, raising or both edges. This last is not true for NMI, where we can detect only
raising or falling edge.
In the following subsections we will focus mainly on IRQ and TPU interrupts. It is due to the fact
that in our Eurobot project we used only these two. Later, in the next chapter, the importance
of these will be shown when I'll tshless motors
works with help of IRQ and how we used TPU interrupt for high frequency repeated procedures.
start with external interrupts IRQ0 to IRQ5. As we already mentioned these are external
interrupts and can be detected by raising, falling or both edges. What does it mean? The answer
is very easy. If we want to generate one or all of these interrupts we must physically connect
electrical lines (voltage/current sources) to proper pins. In this case these are: PORT12 for IRQ0,
PORT14 for IRQ1, PF0 for IRQ2, PF3 for IRQ3, P32 for IRQ4 and P35 for IRQ5. Of course this is not
everything. We also need to enable those interrupts using IER register. Here switching on and
off proper bits we can decide which interrupts should be enabled and which should stay
disabled. As I said at begin, it is possible to assign priority to these interrupts. We can do it very
easily using following registers: IPRA for IRQ0 and IRQ1, and IPRB for IRQ2, IRQ3, IRQ4 and IRQ5.
In this second case we see that unfortunately it is not possible to set up different priorities for
IRQ2 and IRQ3 and additionally IRQ4 and IRQ5. In other words, it means that IRQ2 and IRQ3 will
always have the same priority. The same limitation is for IRQ4 and IRQ5. To make detection of
edge, we need to set up properly two registers: ISCRH and ISCRL. Several pairs of two bits in
these two registers are responsible for selecting which kind of edge we want to detect through
proper interrupts. It is important to note, that always after finishing our interrupt routine we
need to clear proper bit in ISR register. Only this allows accept/detect new interrupt.
TPU is 16-bit timer pulse unit which can be regarded as special kind of internal interrupt.
H8S/2638 has 6 TPU channels with numeration from 0 to 5. It can work in several different
ways: as normal counter compare match, input capture or phase counting (channels 1, 2, 4, 5)
and additionally in synchronous way. TPU can give different outputs: 0, 1, toggle or PWM. It is
also possible to set up buffer operation for channels 0 and 3. Going further we can connect two
channels for example 2 and 5 or 1 and 4 to work in cascade mode. Thanks that we can get one
or two 32-bit counters. To show the strongest side of this unit, we need to point out that there
is the total sum of 26 interrupt sources. This is thanks compare match, input capture, overflow
and underflow interrupt request. Although not all of these are possible for every channel,
making several combinations we can get powerful tool for motion control. To make it little bit
more clearly for a reader I'll try to shortly describe all of the channels.