Technical information

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4.2
4.24.2
4.2 Access Status
Access StatusAccess Status
Access Status
Table 4.2 lists the parameters for access status (Status) that can be specified with HDI command
line interface or displayed as trace results.
Table 4.2 Access Status Parameters
HDI Parameter
(Trace Display) Access Status Description
dmac
(DMAC)
On-chip DMAC Access by the MCU's DMAC
dtc
(DTC)
On-chip DTC Access by the MCU's DTC
refresh
(REFRESH)
Refresh Refresh cycle by the MCU's refresh
controller
prefetch
(PROG)
CPU prefetch Instruction prefetch cycle by the CPU
data
(DATA)
CPU data access Data access for instruction execution
by the CPU
4.3
4.34.3
4.3 I/O Module Selection
I/O Module SelectionI/O Module Selection
I/O Module Selection
Table 4.3 lists the I/O modules that can be selected as Custom settings in the HDI command line
interface.
Table 4.3 I/O Modules
HDI Parameter I/O Module
refresh MCU's refresh controller (MCR, DRAMCR, RTCNT, and RTCOR).
dmac MCU's DMAC.
sci2 Serial communication interface 2 (SCI2). SCI0 and SCI1 are always
enabled.
mult Set SCI1 and SCI2 to support the multiprocessor communication/smart
card interface. SCI0 is always enabled.
tpu 16-bit timer pulse unit 3 to 5 (TPU3 to TPU5).
TPU0 to TPU2 are always enabled.