Hardware manual

Microcomputer Technical Q&A
71
Q&A No.: QAH8S-201
Category: DMAC
Subject: Number of States between Transfers
Question
A minimum of two states are necessary between the first DMAC transfer and the next. Why is
this?
Answer
When the DMAC is activated, the bus request signal is sent to the bus controller at the rise of the
first clock, and enabling is accepted at the fall. At the rise of the next clock, a read/write request is
sent to the bus controller. This operation requires two cycles = two states for the bus cycle.
Applicable Products
Applicability Series Applicability Series Applicability Series
Entire H8S Series Yes H8S/2655 Yes H8S/2350
H8S/2355 Yes H8S/2357 H8S/2345
H8S/2245 H8S/2148 H8S/2144
H8S/2138 H8S/2134 H8S/2128
H8S/2124 — — — —